Simulation Results: lc_ctrl/volatile_unlock_disabled

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.20 %
  • code
  • 83.93 %
  • assert
  • 94.13 %
  • func
  • 92.53 %
  • line
  • 97.12 %
  • branch
  • 93.82 %
  • cond
  • 79.73 %
  • toggle
  • 86.37 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.030s 40.355us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.780s 90.338us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.990s 15.080us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.810s 39.048us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 18.585us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.350s 28.646us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.990s 15.080us 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 18.585us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.740s 372.113us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.330s 1279.054us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.940s 35.465us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.730s 62.082us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.130s 611.734us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.570s 1401.692us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.130s 611.734us 1 1 100.00
lc_ctrl_prog_failure 1.730s 62.082us 1 1 100.00
lc_ctrl_errors 5.570s 1401.692us 1 1 100.00
lc_ctrl_security_escalation 4.840s 1391.642us 1 1 100.00
lc_ctrl_jtag_state_failure 54.110s 23800.946us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.580s 403.731us 1 1 100.00
lc_ctrl_jtag_errors 50.190s 5665.739us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.050s 304.138us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.220s 2135.157us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.580s 403.731us 1 1 100.00
lc_ctrl_jtag_errors 50.190s 5665.739us 1 1 100.00
lc_ctrl_jtag_access 4.150s 368.433us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.820s 713.921us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.290s 408.393us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.390s 73.826us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.500s 1217.009us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.400s 5277.117us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.060s 86.458us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.490s 51.079us 1 1 100.00
lc_ctrl_jtag_alert_test 1.580s 66.628us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.930s 123.487us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.910s 13.697us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 131.810s 83982.235us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.400s 36.258us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.090s 233.248us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.090s 233.248us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 90.338us 1 1 100.00
lc_ctrl_csr_rw 0.990s 15.080us 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 18.585us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.740s 47.743us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 90.338us 1 1 100.00
lc_ctrl_csr_rw 0.990s 15.080us 1 1 100.00
lc_ctrl_csr_aliasing 1.210s 18.585us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.740s 47.743us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 9.200s 5836.508us 1 1 100.00
lc_ctrl_tl_intg_err 4.020s 134.107us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 4.020s 134.107us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.330s 1279.054us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.130s 611.734us 1 1 100.00
lc_ctrl_sec_cm 9.200s 5836.508us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.130s 611.734us 1 1 100.00
lc_ctrl_sec_cm 9.200s 5836.508us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.130s 611.734us 1 1 100.00
lc_ctrl_sec_cm 9.200s 5836.508us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.130s 611.734us 1 1 100.00
lc_ctrl_sec_cm 9.200s 5836.508us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.130s 611.734us 1 1 100.00
lc_ctrl_sec_cm 9.200s 5836.508us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.130s 611.734us 1 1 100.00
lc_ctrl_sec_cm 9.200s 5836.508us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.130s 611.734us 1 1 100.00
lc_ctrl_sec_cm 9.200s 5836.508us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.130s 611.734us 1 1 100.00
lc_ctrl_sec_cm 9.200s 5836.508us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.840s 1391.642us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.740s 372.113us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.220s 2135.157us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.050s 1151.171us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.050s 1151.171us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.200s 245.224us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.430s 661.407us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.430s 661.407us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 16.750s 1616.320us 1 1 100.00