Simulation Results: lc_ctrl/volatile_unlock_enabled

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.58 %
  • code
  • 84.37 %
  • assert
  • 94.13 %
  • func
  • 93.24 %
  • line
  • 97.06 %
  • branch
  • 93.62 %
  • cond
  • 79.49 %
  • toggle
  • 87.21 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.330s 79.412us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 67.537us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.140s 13.539us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.090s 436.666us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 73.727us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.100s 30.474us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.140s 13.539us 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 73.727us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.830s 78.453us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 13.250s 606.460us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.740s 57.736us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.440s 19.087us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.520s 506.183us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.950s 350.658us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.520s 506.183us 1 1 100.00
lc_ctrl_prog_failure 1.440s 19.087us 1 1 100.00
lc_ctrl_errors 5.950s 350.658us 1 1 100.00
lc_ctrl_security_escalation 8.530s 2180.279us 1 1 100.00
lc_ctrl_jtag_state_failure 20.480s 2973.884us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.040s 1350.303us 1 1 100.00
lc_ctrl_jtag_errors 31.030s 71562.693us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.340s 747.084us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.930s 616.997us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.040s 1350.303us 1 1 100.00
lc_ctrl_jtag_errors 31.030s 71562.693us 1 1 100.00
lc_ctrl_jtag_access 9.360s 614.057us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.250s 5493.666us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.370s 96.646us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.060s 36.204us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 31.400s 6670.485us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.430s 189.053us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.150s 40.902us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.570s 500.614us 1 1 100.00
lc_ctrl_jtag_alert_test 1.820s 291.148us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.200s 595.700us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.970s 52.897us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 41.650s 16233.994us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.270s 22.265us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.120s 212.305us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.120s 212.305us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 67.537us 1 1 100.00
lc_ctrl_csr_rw 1.140s 13.539us 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 73.727us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.460s 76.070us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 67.537us 1 1 100.00
lc_ctrl_csr_rw 1.140s 13.539us 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 73.727us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.460s 76.070us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.320s 228.262us 1 1 100.00
lc_ctrl_tl_intg_err 1.650s 92.702us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.650s 92.702us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 13.250s 606.460us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.520s 506.183us 1 1 100.00
lc_ctrl_sec_cm 6.320s 228.262us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.520s 506.183us 1 1 100.00
lc_ctrl_sec_cm 6.320s 228.262us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.520s 506.183us 1 1 100.00
lc_ctrl_sec_cm 6.320s 228.262us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.520s 506.183us 1 1 100.00
lc_ctrl_sec_cm 6.320s 228.262us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.520s 506.183us 1 1 100.00
lc_ctrl_sec_cm 6.320s 228.262us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.520s 506.183us 1 1 100.00
lc_ctrl_sec_cm 6.320s 228.262us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.520s 506.183us 1 1 100.00
lc_ctrl_sec_cm 6.320s 228.262us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.520s 506.183us 1 1 100.00
lc_ctrl_sec_cm 6.320s 228.262us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.530s 2180.279us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.830s 78.453us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.930s 616.997us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.870s 293.780us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.870s 293.780us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.490s 1277.948us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.850s 1222.614us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.850s 1222.614us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 24.290s 6662.354us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 59468857487362744572302962850849438981225355150394800517147321343862010588581 10111
UVM_INFO @ 6662353634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---