Simulation Results: otbn

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.98 %
  • code
  • 95.35 %
  • assert
  • 89.57 %
  • func
  • 97.03 %
  • block
  • 99.41 %
  • line
  • 99.58 %
  • branch
  • 92.44 %
  • toggle
  • 91.96 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
92.86%
V2S
92.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 79.560us 1 1 100.00
single_binary 1 1 100.00
otbn_single 9.000s 31.954us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 21.874us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 19.298us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 27.974us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 47.909us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 147.224us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 19.298us 1 1 100.00
otbn_csr_aliasing 4.000s 47.909us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 43.000s 9566.809us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 22.000s 353.833us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 18.000s 429.456us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 40.000s 1042.469us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 125.000s 2046.553us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 35.000s 252.845us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 6.000s 58.363us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 4.000s 21.697us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 76.408us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 8.000s 31.379us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 23.725us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 102.815us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 102.815us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 21.874us 1 1 100.00
otbn_csr_rw 4.000s 19.298us 1 1 100.00
otbn_csr_aliasing 4.000s 47.909us 1 1 100.00
otbn_same_csr_outstanding 4.000s 21.719us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 21.874us 1 1 100.00
otbn_csr_rw 4.000s 19.298us 1 1 100.00
otbn_csr_aliasing 4.000s 47.909us 1 1 100.00
otbn_same_csr_outstanding 4.000s 21.719us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 41.050us 1 1 100.00
otbn_dmem_err 9.000s 32.219us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 10.000s 197.934us 1 1 100.00
otbn_controller_ispr_rdata_err 11.000s 358.647us 1 1 100.00
otbn_mac_bignum_acc_err 8.000s 53.753us 1 1 100.00
otbn_urnd_err 6.000s 16.384us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 4.000s 58.920us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 57.016us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 32.895us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 172.000s 970.577us 1 1 100.00
otbn_tl_intg_err 9.000s 82.046us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 21.000s 122.879us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 172.000s 970.577us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 172.000s 970.577us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 79.560us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 9.000s 32.219us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 41.050us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 9.000s 82.046us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 58.363us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 41.050us 1 1 100.00
otbn_dmem_err 9.000s 32.219us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 21.697us 0 1 0.00
otbn_illegal_mem_acc 4.000s 58.920us 1 1 100.00
otbn_sec_cm 172.000s 970.577us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 172.000s 970.577us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 9.000s 31.954us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 41.050us 1 1 100.00
otbn_dmem_err 9.000s 32.219us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 21.697us 0 1 0.00
otbn_illegal_mem_acc 4.000s 58.920us 1 1 100.00
otbn_sec_cm 172.000s 970.577us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 172.000s 970.577us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 58.363us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 41.050us 1 1 100.00
otbn_dmem_err 9.000s 32.219us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 21.697us 0 1 0.00
otbn_illegal_mem_acc 4.000s 58.920us 1 1 100.00
otbn_sec_cm 172.000s 970.577us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 172.000s 970.577us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 9.000s 31.954us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 5.000s 38.875us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 18.741us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 45.000s 195.779us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 45.000s 195.779us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 6.000s 17.436us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 172.000s 970.577us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 172.000s 970.577us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 55.324us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 172.000s 970.577us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 172.000s 970.577us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 5.000s 30.859us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 5.000s 30.859us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 29.433us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 31.954us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 31.954us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 9.000s 31.954us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 125.000s 2046.553us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 9.000s 31.954us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 9.000s 31.954us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 8.000s 16.052us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 9.000s 31.954us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 172.000s 970.577us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 281.000s 3430.464us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 33.967us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_zero_state_err_urnd 48394085256287799024492858204216155708078801738101966719752992678036110537259 103
UVM_INFO @ 21697068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_urnd_err 105333725306108280788630436941814507472720770244962318620791183863990466246324 112
UVM_INFO @ 16384207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---