Simulation Results: otp_ctrl

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.20 %
  • code
  • 79.24 %
  • assert
  • 94.11 %
  • func
  • 67.25 %
  • line
  • 88.82 %
  • branch
  • 84.35 %
  • cond
  • 92.40 %
  • toggle
  • 86.87 %
  • FSM
  • 43.75 %
Validation stages
V1
100.00%
V2
90.00%
V2S
77.78%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.740s 733.738us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 7.110s 748.684us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.720s 191.663us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.620s 94.841us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.350s 224.393us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.650s 1569.466us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.800s 111.695us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.620s 94.841us 1 1 100.00
otp_ctrl_csr_aliasing 3.650s 1569.466us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.140s 73.933us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.280s 76.097us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.380s 731.451us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.430s 248.510us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 14.860s 740.826us 1 1 100.00
otp_ctrl_check_fail 3.070s 175.213us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 2.870s 140.460us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 5.110s 457.612us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 7.370s 1040.637us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 12.440s 1481.940us 1 1 100.00
otp_ctrl_parallel_lc_esc 8.180s 237.711us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 7.950s 262.055us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 1.470s 196.405us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 23.930s 15318.582us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 56.740s 17622.083us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.290s 135.816us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.780s 122.831us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.500s 116.991us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.500s 116.991us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.720s 191.663us 1 1 100.00
otp_ctrl_csr_rw 1.620s 94.841us 1 1 100.00
otp_ctrl_csr_aliasing 3.650s 1569.466us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.840s 280.722us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.720s 191.663us 1 1 100.00
otp_ctrl_csr_rw 1.620s 94.841us 1 1 100.00
otp_ctrl_csr_aliasing 3.650s 1569.466us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.840s 280.722us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
otp_ctrl_tl_intg_err 13.150s 1246.659us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 13.150s 1246.659us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 7.110s 748.684us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 7.110s 748.684us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.180s 237.711us 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.180s 237.711us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.180s 237.711us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 8.180s 237.711us 1 1 100.00
otp_ctrl_macro_errs 1.470s 196.405us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.180s 237.711us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.180s 237.711us 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.180s 237.711us 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.180s 237.711us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.180s 237.711us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 8.180s 237.711us 1 1 100.00
otp_ctrl_macro_errs 1.470s 196.405us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.180s 237.711us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.180s 237.711us 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.430s 248.510us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.070s 175.213us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 5.110s 457.612us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 5.110s 457.612us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 5.110s 457.612us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 5.110s 457.612us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 5.110s 457.612us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 7.110s 748.684us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 5.110s 457.612us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 7.110s 748.684us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 116.740s 11033.661us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 2.870s 140.460us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 7.110s 748.684us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 7.110s 748.684us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 1.470s 196.405us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.120s 5897.444us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
otp_ctrl_stress_all_with_rand_reset 56.820s 11562.187us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 65479701620486841218370554890624697687639818121558533633346634177168500705870 3085
UVM_INFO @ 175212939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 105615271989839544991822796313688965160293920270348285783060880343593448555325 503
UVM_INFO @ 196405339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---