Simulation Results: pwrmgr

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.11 %
  • code
  • 94.47 %
  • assert
  • 96.34 %
  • func
  • 97.53 %
  • line
  • 98.92 %
  • branch
  • 95.61 %
  • cond
  • 93.78 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
80.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.760s 24.193us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.670s 27.022us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.710s 36.965us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.520s 741.910us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.200s 23.802us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.240s 46.361us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.710s 36.965us 1 1 100.00
pwrmgr_csr_aliasing 1.200s 23.802us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.980s 344.045us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.980s 344.045us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.920s 38.205us 1 1 100.00
pwrmgr_lowpower_invalid 0.710s 44.206us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 1.080s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 1.210s 103.410us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 1.080s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.970s 324.781us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.830s 44.031us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.670s 38.836us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.410s 1526.532us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.640s 27.254us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.180s 732.099us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.180s 732.099us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.670s 27.022us 1 1 100.00
pwrmgr_csr_rw 0.710s 36.965us 1 1 100.00
pwrmgr_csr_aliasing 1.200s 23.802us 1 1 100.00
pwrmgr_same_csr_outstanding 0.690s 43.247us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.670s 27.022us 1 1 100.00
pwrmgr_csr_rw 0.710s 36.965us 1 1 100.00
pwrmgr_csr_aliasing 1.200s 23.802us 1 1 100.00
pwrmgr_same_csr_outstanding 0.690s 43.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.680s 14.336us 0 1 0.00
pwrmgr_sec_cm 0.680s 10.245us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.680s 10.245us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.680s 10.245us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.680s 14.336us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.290s 754.957us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.970s 324.781us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.730s 64.800us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.660s 40.366us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.680s 10.245us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.680s 10.245us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.680s 10.245us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.720s 47.385us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.680s 52.357us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.990s 218.024us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.710s 36.965us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.710s 36.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.840s 97.236us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 11.330s 5040.639us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
pwrmgr_reset 85302736833804738140078924831863442383974372701374708104127140356880188073849 149
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)'
pwrmgr_escalation_timeout 52164596213260026194044870588177273710267794579032649426224801478606418830905 79
UVM_ERROR @ 97235752 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 97235752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_tl_intg_err 10130378907653177250554719733834677750660021747254131233981621573808355635101 85
UVM_INFO @ 14336164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 97290707708040952370139831600418983660766097935102656942818423038127075169122 77
UVM_INFO @ 10245430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---