Simulation Results: rom_ctrl/32kb

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.74 %
  • code
  • 93.51 %
  • assert
  • 96.80 %
  • func
  • 96.90 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 95.54 %
  • toggle
  • 99.97 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.410s 184.507us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.040s 226.438us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.220s 558.498us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.520s 774.001us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.630s 164.184us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.390s 407.951us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.220s 558.498us 1 1 100.00
rom_ctrl_csr_aliasing 4.630s 164.184us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.570s 1027.810us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.600s 160.431us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.950s 182.483us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 15.320s 580.080us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.880s 970.467us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.080s 170.049us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.370s 602.927us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.370s 602.927us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.040s 226.438us 1 1 100.00
rom_ctrl_csr_rw 5.220s 558.498us 1 1 100.00
rom_ctrl_csr_aliasing 4.630s 164.184us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.530s 2089.247us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.040s 226.438us 1 1 100.00
rom_ctrl_csr_rw 5.220s 558.498us 1 1 100.00
rom_ctrl_csr_aliasing 4.630s 164.184us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.530s 2089.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 6.310s 186.415us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.980s 1652.614us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 194.230s 610.226us 1 1 100.00
rom_ctrl_tl_intg_err 25.210s 1475.063us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 194.230s 610.226us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 194.230s 610.226us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 6.310s 186.415us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 6.310s 186.415us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 6.310s 186.415us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 6.310s 186.415us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 6.310s 186.415us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 194.230s 610.226us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 194.230s 610.226us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.410s 184.507us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.410s 184.507us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.410s 184.507us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 25.210s 1475.063us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 6.310s 186.415us 0 1 0.00
rom_ctrl_kmac_err_chk 5.880s 970.467us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 6.310s 186.415us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 6.310s 186.415us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 6.310s 186.415us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.980s 1652.614us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 194.230s 610.226us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 319.620s 16632.580us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 60854290200115461098800648428852474597490492291920478677284093913948375145486 80
UVM_INFO @ 186415447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---