Simulation Results: rom_ctrl/64kb

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.85 %
  • code
  • 96.62 %
  • assert
  • 96.80 %
  • func
  • 97.14 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 97.77 %
  • toggle
  • 99.95 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.630s 1253.688us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.020s 2862.556us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.850s 209.126us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.060s 214.599us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.780s 386.502us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.490s 223.408us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.850s 209.126us 1 1 100.00
rom_ctrl_csr_aliasing 6.780s 386.502us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.240s 627.538us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.310s 907.480us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.700s 559.913us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 31.770s 4201.363us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.560s 544.736us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.700s 1029.101us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.960s 216.525us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.960s 216.525us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.020s 2862.556us 1 1 100.00
rom_ctrl_csr_rw 5.850s 209.126us 1 1 100.00
rom_ctrl_csr_aliasing 6.780s 386.502us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.320s 303.434us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.020s 2862.556us 1 1 100.00
rom_ctrl_csr_rw 5.850s 209.126us 1 1 100.00
rom_ctrl_csr_aliasing 6.780s 386.502us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.320s 303.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 77.230s 4178.973us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.050s 1067.817us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 455.070s 825.662us 1 1 100.00
rom_ctrl_tl_intg_err 94.530s 1389.961us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 455.070s 825.662us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 455.070s 825.662us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 77.230s 4178.973us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 77.230s 4178.973us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 77.230s 4178.973us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 77.230s 4178.973us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 77.230s 4178.973us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 455.070s 825.662us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 455.070s 825.662us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.630s 1253.688us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.630s 1253.688us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.630s 1253.688us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 94.530s 1389.961us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 77.230s 4178.973us 1 1 100.00
rom_ctrl_kmac_err_chk 14.560s 544.736us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 77.230s 4178.973us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 77.230s 4178.973us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 77.230s 4178.973us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.050s 1067.817us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 455.070s 825.662us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 88.020s 3468.279us 1 1 100.00