Simulation Results: rstmgr

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.44 %
  • code
  • 99.20 %
  • assert
  • 97.86 %
  • func
  • 98.26 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.40 %
  • toggle
  • 99.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.250s 253.664us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.870s 135.150us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.710s 65.944us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 6.040s 1565.793us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.360s 203.904us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.830s 105.371us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.710s 65.944us 1 1 100.00
rstmgr_csr_aliasing 1.360s 203.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.880s 116.161us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.360s 145.238us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.040s 183.204us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.840s 1399.870us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.840s 1399.870us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.840s 1399.870us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.840s 1399.870us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 33.690s 13182.425us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.890s 80.368us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.510s 145.405us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.510s 145.405us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.870s 135.150us 1 1 100.00
rstmgr_csr_rw 0.710s 65.944us 1 1 100.00
rstmgr_csr_aliasing 1.360s 203.904us 1 1 100.00
rstmgr_same_csr_outstanding 0.860s 81.082us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.870s 135.150us 1 1 100.00
rstmgr_csr_rw 0.710s 65.944us 1 1 100.00
rstmgr_csr_aliasing 1.360s 203.904us 1 1 100.00
rstmgr_same_csr_outstanding 0.860s 81.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 19.350s 17163.913us 1 1 100.00
rstmgr_tl_intg_err 3.200s 950.585us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 19.350s 17163.913us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 19.350s 17163.913us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.200s 950.585us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.160s 187.076us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.630s 1975.997us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.200s 302.042us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 19.350s 17163.913us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.710s 65.944us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.710s 65.944us 1 1 100.00