Simulation Results: rv_timer

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.53 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 86.76 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.790s 925.277us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.570s 53.777us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.590s 50.964us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.580s 149.532us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.730s 37.180us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.820s 21.369us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.590s 50.964us 1 1 100.00
rv_timer_csr_aliasing 0.730s 37.180us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.760s 2370.843us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.200s 1697.191us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 56.290s 43189.934us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 56.290s 43189.934us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.850s 6054.293us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.650s 28.323us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.670s 16.479us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.640s 618.474us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.640s 618.474us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.570s 53.777us 1 1 100.00
rv_timer_csr_rw 0.590s 50.964us 1 1 100.00
rv_timer_csr_aliasing 0.730s 37.180us 1 1 100.00
rv_timer_same_csr_outstanding 0.800s 38.164us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.570s 53.777us 1 1 100.00
rv_timer_csr_rw 0.590s 50.964us 1 1 100.00
rv_timer_csr_aliasing 0.730s 37.180us 1 1 100.00
rv_timer_same_csr_outstanding 0.800s 38.164us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.940s 292.287us 1 1 100.00
rv_timer_tl_intg_err 1.260s 517.578us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.260s 517.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.100s 192.025us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.630s 407.358us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 11.560s 4681.805us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 11101228840136759892785538633665387184162896780735246957935337340728198916782 75
UVM_INFO @ 192025189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 60826745722085393216051223131631217377048954188145019080064391574373091105906 75
UVM_INFO @ 2370842824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 39365868969560176853999715893974604125197377391749990668853362939865326558644 75
UVM_INFO @ 407358330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---