Simulation Results: spi_device/1r1w

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.75 %
  • code
  • 93.29 %
  • assert
  • 94.64 %
  • func
  • 60.32 %
  • line
  • 99.05 %
  • branch
  • 98.23 %
  • cond
  • 96.29 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 31.440s 2152.417us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.060s 115.124us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.770s 235.244us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 18.390s 3481.505us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 15.160s 1349.479us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.250s 334.654us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.770s 235.244us 1 1 100.00
spi_device_csr_aliasing 15.160s 1349.479us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.760s 12.740us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.700s 24.837us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.720s 122.631us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.990s 1.189us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.700s 3.707us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.850s 47.910us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.850s 47.910us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 15.940s 19320.357us 1 1 100.00
spi_device_tpm_sts_read 0.730s 152.647us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 0.660s 21.074us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 1.770s 29.489us 1 1 100.00
spi_device_flash_all 14.340s 16808.758us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.680s 803.846us 1 1 100.00
spi_device_flash_all 14.340s 16808.758us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 2.680s 803.846us 1 1 100.00
spi_device_flash_all 14.340s 16808.758us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 14.340s 16808.758us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 11.550s 4586.756us 1 1 100.00
spi_device_flash_all 14.340s 16808.758us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 11.550s 4586.756us 1 1 100.00
spi_device_flash_all 14.340s 16808.758us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 11.550s 4586.756us 1 1 100.00
spi_device_flash_all 14.340s 16808.758us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 11.550s 4586.756us 1 1 100.00
spi_device_flash_all 14.340s 16808.758us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 11.550s 4586.756us 1 1 100.00
spi_device_flash_all 14.340s 16808.758us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 16.470s 6683.054us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 39.450s 15493.813us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 39.450s 15493.813us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 39.450s 15493.813us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 11.740s 1099.549us 1 1 100.00
spi_device_read_buffer_direct 10.190s 983.792us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 39.450s 15493.813us 1 1 100.00
spi_device_flash_all 14.340s 16808.758us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 14.340s 16808.758us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 14.340s 16808.758us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 6.570s 1841.932us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 6.570s 1841.932us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 31.440s 2152.417us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 158.390s 101346.703us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 1.050s 137.278us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.720s 18.101us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.890s 155.906us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.800s 214.372us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.800s 214.372us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.060s 115.124us 1 1 100.00
spi_device_csr_rw 1.770s 235.244us 1 1 100.00
spi_device_csr_aliasing 15.160s 1349.479us 1 1 100.00
spi_device_same_csr_outstanding 1.430s 29.929us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.060s 115.124us 1 1 100.00
spi_device_csr_rw 1.770s 235.244us 1 1 100.00
spi_device_csr_aliasing 15.160s 1349.479us 1 1 100.00
spi_device_same_csr_outstanding 1.430s 29.929us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.410s 93.014us 1 1 100.00
spi_device_tl_intg_err 6.540s 262.318us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 6.540s 262.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 261.350s 469425.472us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 81138719391149802284905669390708366116201700449394607517800837933285862280802 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1009087 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1009087 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[936])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 71893794016917878857931688833736029410780231630773461244931759630867099099404 76
UVM_ERROR @ 1232392 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x564d1d [10101100100110100011101] vs 0x0 [0])
UVM_ERROR @ 1256392 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x74b2ee [11101001011001011101110] vs 0x0 [0])
UVM_ERROR @ 1257392 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8008c0 [100000000000100011000000] vs 0x0 [0])
UVM_ERROR @ 1296392 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7d1d2d [11111010001110100101101] vs 0x0 [0])