Simulation Results: spi_device/2p

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.67 %
  • code
  • 94.12 %
  • assert
  • 94.49 %
  • func
  • 62.40 %
  • line
  • 99.13 %
  • branch
  • 98.40 %
  • cond
  • 95.96 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 217.570s 166228.450us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.170s 27.331us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.280s 173.114us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 9.290s 746.690us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 6.010s 318.399us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.080s 261.033us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.280s 173.114us 1 1 100.00
spi_device_csr_aliasing 6.010s 318.399us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.810s 11.627us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.600s 76.268us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.870s 15.236us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.040s 52.967us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.710s 23.413us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.800s 284.626us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.800s 284.626us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 16.050s 113085.545us 1 1 100.00
spi_device_tpm_sts_read 0.850s 60.146us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 4.990s 2233.994us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.500s 653.934us 1 1 100.00
spi_device_flash_all 49.800s 7791.309us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.760s 325.837us 1 1 100.00
spi_device_flash_all 49.800s 7791.309us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.760s 325.837us 1 1 100.00
spi_device_flash_all 49.800s 7791.309us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 49.800s 7791.309us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 10.910s 2715.021us 1 1 100.00
spi_device_flash_all 49.800s 7791.309us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 10.910s 2715.021us 1 1 100.00
spi_device_flash_all 49.800s 7791.309us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 10.910s 2715.021us 1 1 100.00
spi_device_flash_all 49.800s 7791.309us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 10.910s 2715.021us 1 1 100.00
spi_device_flash_all 49.800s 7791.309us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 10.910s 2715.021us 1 1 100.00
spi_device_flash_all 49.800s 7791.309us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.160s 393.797us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 11.100s 841.362us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 11.100s 841.362us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 11.100s 841.362us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 24.450s 2344.068us 1 1 100.00
spi_device_read_buffer_direct 15.070s 13503.418us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 11.100s 841.362us 1 1 100.00
spi_device_flash_all 49.800s 7791.309us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 49.800s 7791.309us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 49.800s 7791.309us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.040s 105.134us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.040s 105.134us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 217.570s 166228.450us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 51.200s 7710.865us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 1.050s 480.484us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.820s 54.954us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.780s 12.339us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.950s 137.945us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.950s 137.945us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.170s 27.331us 1 1 100.00
spi_device_csr_rw 1.280s 173.114us 1 1 100.00
spi_device_csr_aliasing 6.010s 318.399us 1 1 100.00
spi_device_same_csr_outstanding 2.930s 430.166us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.170s 27.331us 1 1 100.00
spi_device_csr_rw 1.280s 173.114us 1 1 100.00
spi_device_csr_aliasing 6.010s 318.399us 1 1 100.00
spi_device_same_csr_outstanding 2.930s 430.166us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.360s 93.100us 1 1 100.00
spi_device_tl_intg_err 5.040s 360.396us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.040s 360.396us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 61.750s 12290.944us 1 1 100.00