Simulation Results: spi_host

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.56 %
  • code
  • 94.88 %
  • assert
  • 94.13 %
  • func
  • 88.66 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 92.95 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 46.000s 2979.065us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 18.007us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 45.886us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 918.033us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 91.813us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 37.985us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 45.886us 1 1 100.00
spi_host_csr_aliasing 1.000s 91.813us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 40.530us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 20.629us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 97.222us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 75.683us 1 1 100.00
spi_host_error_cmd 2.000s 27.205us 1 1 100.00
spi_host_event 13.000s 1261.723us 1 1 100.00
clock_rate 0 1 0.00
spi_host_speed 20.000s 10035.211us 0 1 0.00
speed 0 1 0.00
spi_host_speed 20.000s 10035.211us 0 1 0.00
chip_select_timing 0 1 0.00
spi_host_speed 20.000s 10035.211us 0 1 0.00
sw_reset 1 1 100.00
spi_host_sw_reset 38.000s 2105.453us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 431.451us 1 1 100.00
cpol_cpha 0 1 0.00
spi_host_speed 20.000s 10035.211us 0 1 0.00
full_cycle 0 1 0.00
spi_host_speed 20.000s 10035.211us 0 1 0.00
duplex 1 1 100.00
spi_host_smoke 46.000s 2979.065us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 46.000s 2979.065us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 3.000s 121.303us 1 1 100.00
spien 1 1 100.00
spi_host_spien 13.000s 562.724us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 17.000s 4303.538us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 1.000s 406.532us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 75.683us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 48.999us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 18.846us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 91.804us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 91.804us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 18.007us 1 1 100.00
spi_host_csr_rw 1.000s 45.886us 1 1 100.00
spi_host_csr_aliasing 1.000s 91.813us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 31.513us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 18.007us 1 1 100.00
spi_host_csr_rw 1.000s 45.886us 1 1 100.00
spi_host_csr_aliasing 1.000s 91.813us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 31.513us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 101.135us 1 1 100.00
spi_host_sec_cm 1.000s 156.134us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 101.135us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 116.000s 8523.554us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=*
spi_host_speed 93354741843196744177093722561462787594916380422991825833843222627666423870269 241
UVM_INFO @ 10035210910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---