Simulation Results: sram_ctrl/main

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.68 %
  • code
  • 96.04 %
  • assert
  • 96.19 %
  • func
  • 91.80 %
  • block
  • 95.07 %
  • line
  • 95.70 %
  • branch
  • 92.38 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 2404.395us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 36.624us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.528us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 94.301us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.066us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 383.904us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 20.528us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.066us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 115.000s 15674.647us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 88.000s 8970.877us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 17.000s 7389.126us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 159.000s 16489.554us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 162.000s 56438.391us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 49.000s 11887.146us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 28.000s 7790.159us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 23.000s 35869.999us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 2947.452us 1 1 100.00
sram_ctrl_partial_access_b2b 136.000s 4531.764us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 687.582us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 1337.997us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 2317.541us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 5.000s 1390.183us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 3738.923us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 105.000s 27189.248us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 44.717us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 25.072us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 25.072us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 36.624us 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.528us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.066us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 79.299us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 36.624us 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.528us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.066us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 79.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 7824.424us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 347.743us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 179.466us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 347.743us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 179.466us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 1390.183us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 1390.183us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 20.528us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 23.000s 35869.999us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 23.000s 35869.999us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 23.000s 35869.999us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 28.000s 7790.159us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 1346.084us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 7824.424us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 8.000s 1427.165us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 2404.395us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 2404.395us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 23.000s 35869.999us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 347.743us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 28.000s 7790.159us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 347.743us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 347.743us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 2404.395us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 347.743us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 11.000s 361.676us 1 1 100.00