Simulation Results: sysrst_ctrl

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.19 %
  • code
  • 89.30 %
  • assert
  • 88.12 %
  • func
  • 66.14 %
  • line
  • 95.22 %
  • branch
  • 95.96 %
  • cond
  • 92.75 %
  • toggle
  • 99.77 %
  • FSM
  • 62.82 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.610s 2111.864us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.210s 2523.738us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.660s 2229.433us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.660s 2310.581us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 11.570s 6037.647us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.660s 2052.033us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 50.950s 41538.540us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.170s 2772.793us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.750s 2046.786us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.660s 2052.033us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.170s 2772.793us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 112.850s 61639.931us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 122.530s 63565.772us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.620s 3576.211us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.870s 3202.837us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.940s 2510.605us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 3.630s 2269.092us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 9.720s 4683.253us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.420s 2640.123us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 6.020s 6437.718us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 44.020s 35560.006us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 52.730s 107880.210us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.560s 2033.403us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.590s 2017.892us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.060s 2157.372us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.060s 2157.372us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 11.570s 6037.647us 1 1 100.00
sysrst_ctrl_csr_rw 2.660s 2052.033us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.170s 2772.793us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.040s 4355.968us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 11.570s 6037.647us 1 1 100.00
sysrst_ctrl_csr_rw 2.660s 2052.033us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.170s 2772.793us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.040s 4355.968us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 11.620s 22107.301us 1 1 100.00
sysrst_ctrl_tl_intg_err 60.080s 42392.372us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 60.080s 42392.372us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 4.840s 4647.119us 1 1 100.00