Simulation Results: uart

 
23/04/2026 15:30:30 DVSim: v1.32.0 sha: a82c489 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.73 %
  • code
  • 95.14 %
  • assert
  • 97.12 %
  • func
  • 52.93 %
  • line
  • 99.17 %
  • branch
  • 96.97 %
  • cond
  • 92.88 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 10.160s 5464.591us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.690s 30.030us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.690s 18.981us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.320s 137.623us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.800s 108.738us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.200s 24.754us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.690s 18.981us 1 1 100.00
uart_csr_aliasing 0.800s 108.738us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 39.910s 46123.430us 1 1 100.00
parity 2 2 100.00
uart_smoke 10.160s 5464.591us 1 1 100.00
uart_tx_rx 39.910s 46123.430us 1 1 100.00
parity_error 2 2 100.00
uart_intr 20.630s 19868.324us 1 1 100.00
uart_rx_parity_err 124.270s 116546.203us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 39.910s 46123.430us 1 1 100.00
uart_intr 20.630s 19868.324us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 43.510s 77750.152us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 30.260s 109001.060us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 15.630s 12590.692us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 20.630s 19868.324us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 20.630s 19868.324us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 20.630s 19868.324us 1 1 100.00
perf 1 1 100.00
uart_perf 100.050s 2596.472us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 24.940s 13158.689us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 24.940s 13158.689us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 142.360s 117822.817us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.740s 4529.935us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.400s 818.232us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 2.780s 2005.439us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 217.650s 43819.955us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 187.970s 158807.092us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.700s 33.199us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.670s 29.724us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.420s 201.678us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.420s 201.678us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.690s 30.030us 1 1 100.00
uart_csr_rw 0.690s 18.981us 1 1 100.00
uart_csr_aliasing 0.800s 108.738us 1 1 100.00
uart_same_csr_outstanding 0.800s 29.863us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.690s 30.030us 1 1 100.00
uart_csr_rw 0.690s 18.981us 1 1 100.00
uart_csr_aliasing 0.800s 108.738us 1 1 100.00
uart_same_csr_outstanding 0.800s 29.863us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.820s 441.628us 1 1 100.00
uart_tl_intg_err 1.340s 416.683us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.340s 416.683us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 16.020s 6403.637us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = *
uart_stress_all_with_rand_reset 51826988038763259269641242657739790067395170625282164030399728698578384274012 111
UVM_ERROR @ 4538276868 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 4538436868 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 4538436868 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 4541676868 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0