Simulation Results

Simulation Results: adc_ctrl

27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
65.07 %

code
91.69 %

assert
90.76 %

func
12.77 %

line
98.03 %

branch
96.29 %

cond
85.98 %

toggle
99.76 %

FSM
78.38 %

Validation stages

V1		100.00%
V2		52.63%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	adc_ctrl_smoke	3.770s	5769.852us	1	1	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	1.070s	1105.466us	1	1	100.00
csr_rw				1	1	100.00
	adc_ctrl_csr_rw	1.130s	594.408us	1	1	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	7.540s	29164.536us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	2.210s	840.099us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	1.040s	606.384us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	adc_ctrl_csr_rw	1.130s	594.408us	1	1	100.00
	adc_ctrl_csr_aliasing	2.210s	840.099us	1	1	100.00

10/19 passed

52.63 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	1	0.00
	adc_ctrl_filters_polled	0.900s	504.166us	0	1	0.00
filters_polled_fixed				0	1	0.00
	adc_ctrl_filters_polled_fixed	1.080s	395.484us	0	1	0.00
filters_interrupt				0	1	0.00
	adc_ctrl_filters_interrupt	0.940s	283.335us	0	1	0.00
filters_interrupt_fixed				0	1	0.00
	adc_ctrl_filters_interrupt_fixed	1.010s	476.530us	0	1	0.00
filters_wakeup				0	1	0.00
	adc_ctrl_filters_wakeup	0.760s	501.056us	0	1	0.00
filters_wakeup_fixed				0	1	0.00
	adc_ctrl_filters_wakeup_fixed	0.960s	301.975us	0	1	0.00
filters_both				0	1	0.00
	adc_ctrl_filters_both	0.660s	339.743us	0	1	0.00
clock_gating				0	1	0.00
	adc_ctrl_clock_gating	0.690s	491.720us	0	1	0.00
poweron_counter				1	1	100.00
	adc_ctrl_poweron_counter	4.900s	5308.225us	1	1	100.00
lowpower_counter				1	1	100.00
	adc_ctrl_lowpower_counter	37.490s	24085.524us	1	1	100.00
fsm_reset				1	1	100.00
	adc_ctrl_fsm_reset	86.920s	61897.047us	1	1	100.00
stress_all				0	1	0.00
	adc_ctrl_stress_all	0.950s	817.208us	0	1	0.00
alert_test				1	1	100.00
	adc_ctrl_alert_test	0.770s	532.347us	1	1	100.00
intr_test				1	1	100.00
	adc_ctrl_intr_test	0.850s	346.054us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	adc_ctrl_tl_errors	2.710s	353.537us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	adc_ctrl_tl_errors	2.710s	353.537us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	adc_ctrl_csr_hw_reset	1.070s	1105.466us	1	1	100.00
	adc_ctrl_csr_rw	1.130s	594.408us	1	1	100.00
	adc_ctrl_csr_aliasing	2.210s	840.099us	1	1	100.00
	adc_ctrl_same_csr_outstanding	3.840s	4591.244us	1	1	100.00
tl_d_partial_access				4	4	100.00
	adc_ctrl_csr_hw_reset	1.070s	1105.466us	1	1	100.00
	adc_ctrl_csr_rw	1.130s	594.408us	1	1	100.00
	adc_ctrl_csr_aliasing	2.210s	840.099us	1	1	100.00
	adc_ctrl_same_csr_outstanding	3.840s	4591.244us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	adc_ctrl_sec_cm	11.620s	8003.841us	1	1	100.00
	adc_ctrl_tl_intg_err	3.660s	9018.938us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	adc_ctrl_tl_intg_err	3.660s	9018.938us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	adc_ctrl_stress_all_with_rand_reset	3.450s	749.435us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]
	adc_ctrl_filters_polled	106311656440422278949988042759925668122757264324037881350473874907844377560980	394	UVM_INFO @ 504166185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	19645493711379185424635150218551726479940476878731648182243668385939642906731	394	UVM_INFO @ 395484121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	94430959303351853126680278655778879560398455041872973570451725280413559787991	394	UVM_INFO @ 283335417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	18784471663682084043054933209362549561056657428430752759287623908520058725412	394	UVM_INFO @ 476529790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	100902408892479553249698272905775567385817524506076003123958211957752963563399	394	UVM_INFO @ 501055590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	56576592529270302363843609890734015196787299542986437171018322445189123994800	394	UVM_INFO @ 301974946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	48694345640192905770294256389149973955199770489882627133754307990737694323410	394	UVM_INFO @ 491719900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	93344572575926884861467923763593657153225484181510958886387660305241819317626	394	UVM_INFO @ 339743047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	71063831876649290684677689853789537199924877295494507928553234925165134866836	390	UVM_INFO @ 817207572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---