Simulation Results: aes/masked

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.44 %
  • code
  • 95.27 %
  • assert
  • 98.14 %
  • func
  • 65.90 %
  • block
  • 95.93 %
  • line
  • 97.60 %
  • branch
  • 89.96 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
94.74%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 224.807us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 100.937us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 56.353us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 95.191us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 198.839us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 99.762us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 60.391us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 95.191us 1 1 100.00
aes_csr_aliasing 2.000s 99.762us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 100.937us 1 1 100.00
aes_config_error 3.000s 70.544us 1 1 100.00
aes_stress 5.000s 96.389us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 100.937us 1 1 100.00
aes_config_error 3.000s 70.544us 1 1 100.00
aes_stress 5.000s 96.389us 1 1 100.00
back2back 2 2 100.00
aes_stress 5.000s 96.389us 1 1 100.00
aes_b2b 13.000s 496.019us 1 1 100.00
backpressure 1 1 100.00
aes_stress 5.000s 96.389us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 100.937us 1 1 100.00
aes_config_error 3.000s 70.544us 1 1 100.00
aes_stress 5.000s 96.389us 1 1 100.00
aes_alert_reset 29.000s 10022.661us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 79.676us 1 1 100.00
aes_config_error 3.000s 70.544us 1 1 100.00
aes_alert_reset 29.000s 10022.661us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 80.710us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 183.955us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 7.000s 872.278us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 29.000s 10022.661us 0 1 0.00
stress 1 1 100.00
aes_stress 5.000s 96.389us 1 1 100.00
sideload 2 2 100.00
aes_stress 5.000s 96.389us 1 1 100.00
aes_sideload 6.000s 186.891us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 126.238us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 10.000s 897.123us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 66.125us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 56.331us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 4.000s 153.877us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 4.000s 153.877us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 56.353us 1 1 100.00
aes_csr_rw 2.000s 95.191us 1 1 100.00
aes_csr_aliasing 2.000s 99.762us 1 1 100.00
aes_same_csr_outstanding 3.000s 93.440us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 56.353us 1 1 100.00
aes_csr_rw 2.000s 95.191us 1 1 100.00
aes_csr_aliasing 2.000s 99.762us 1 1 100.00
aes_same_csr_outstanding 3.000s 93.440us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 5.000s 115.952us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 53.000s 10013.285us 0 1 0.00
aes_control_fi 2.000s 47.158us 1 1 100.00
aes_cipher_fi 3.000s 58.401us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 144.737us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 144.737us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 144.737us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 144.737us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 386.987us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 10.000s 1419.184us 1 1 100.00
aes_tl_intg_err 3.000s 202.620us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 202.620us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 29.000s 10022.661us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 144.737us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 144.737us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 100.937us 1 1 100.00
aes_stress 5.000s 96.389us 1 1 100.00
aes_alert_reset 29.000s 10022.661us 0 1 0.00
aes_core_fi 2.000s 154.428us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 66.125us 1 1 100.00
aes_config_error 3.000s 70.544us 1 1 100.00
aes_stress 5.000s 96.389us 1 1 100.00
aes_core_fi 2.000s 154.428us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 144.737us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 77.951us 1 1 100.00
aes_stress 5.000s 96.389us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 5.000s 96.389us 1 1 100.00
aes_sideload 6.000s 186.891us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 77.951us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 77.951us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 77.951us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 77.951us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 77.951us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 5.000s 96.389us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 5.000s 96.389us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 53.000s 10013.285us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 53.000s 10013.285us 0 1 0.00
aes_control_fi 2.000s 47.158us 1 1 100.00
aes_cipher_fi 3.000s 58.401us 1 1 100.00
aes_ctr_fi 1.000s 82.384us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 53.000s 10013.285us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 53.000s 10013.285us 0 1 0.00
aes_control_fi 2.000s 47.158us 1 1 100.00
aes_cipher_fi 3.000s 58.401us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 58.401us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 53.000s 10013.285us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 53.000s 10013.285us 0 1 0.00
aes_control_fi 2.000s 47.158us 1 1 100.00
aes_ctr_fi 1.000s 82.384us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 53.000s 10013.285us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 53.000s 10013.285us 0 1 0.00
aes_control_fi 2.000s 47.158us 1 1 100.00
aes_cipher_fi 3.000s 58.401us 1 1 100.00
aes_ctr_fi 1.000s 82.384us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 29.000s 10022.661us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 53.000s 10013.285us 0 1 0.00
aes_control_fi 2.000s 47.158us 1 1 100.00
aes_cipher_fi 3.000s 58.401us 1 1 100.00
aes_ctr_fi 1.000s 82.384us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 53.000s 10013.285us 0 1 0.00
aes_control_fi 2.000s 47.158us 1 1 100.00
aes_cipher_fi 3.000s 58.401us 1 1 100.00
aes_ctr_fi 1.000s 82.384us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 53.000s 10013.285us 0 1 0.00
aes_control_fi 2.000s 47.158us 1 1 100.00
aes_ctr_fi 1.000s 82.384us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 53.000s 10013.285us 0 1 0.00
aes_ghash_fi 2.000s 52.866us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 53.000s 10013.285us 0 1 0.00
aes_control_fi 2.000s 47.158us 1 1 100.00
aes_cipher_fi 3.000s 58.401us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 38.000s 787.334us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 49003864374871786598234698505135783295710025561318728422782591773998379249002 2860
UVM_INFO @ 10022660548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 49051422253147389217584087988925452876334829246792006694695725953158512191773 482
UVM_INFO @ 10013284572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 108751073139996117959495372670640437938071946568004520340439015260874275323057 1268
UVM_INFO @ 787334171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---