Simulation Results: aes/unmasked

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.07 %
  • code
  • 90.96 %
  • assert
  • 97.75 %
  • func
  • 66.51 %
  • block
  • 91.13 %
  • line
  • 93.39 %
  • branch
  • 83.82 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
89.47%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 96.463us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 74.120us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 61.306us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 54.168us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 599.432us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 208.936us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 98.660us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 54.168us 1 1 100.00
aes_csr_aliasing 3.000s 208.936us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 74.120us 1 1 100.00
aes_config_error 2.000s 90.206us 1 1 100.00
aes_stress 2.000s 114.717us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 74.120us 1 1 100.00
aes_config_error 2.000s 90.206us 1 1 100.00
aes_stress 2.000s 114.717us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 114.717us 1 1 100.00
aes_b2b 5.000s 354.071us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 114.717us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 3.000s 74.120us 1 1 100.00
aes_config_error 2.000s 90.206us 1 1 100.00
aes_stress 2.000s 114.717us 1 1 100.00
aes_alert_reset 7.000s 10062.646us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 91.582us 1 1 100.00
aes_config_error 2.000s 90.206us 1 1 100.00
aes_alert_reset 7.000s 10062.646us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 112.587us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 307.942us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 5.000s 295.238us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 7.000s 10062.646us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 114.717us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 114.717us 1 1 100.00
aes_sideload 3.000s 143.049us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 303.319us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 38.000s 10141.835us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 57.414us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 63.820us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 127.481us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 127.481us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 61.306us 1 1 100.00
aes_csr_rw 2.000s 54.168us 1 1 100.00
aes_csr_aliasing 3.000s 208.936us 1 1 100.00
aes_same_csr_outstanding 3.000s 108.084us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 61.306us 1 1 100.00
aes_csr_rw 2.000s 54.168us 1 1 100.00
aes_csr_aliasing 3.000s 208.936us 1 1 100.00
aes_same_csr_outstanding 3.000s 108.084us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 89.518us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 11.000s 10047.233us 0 1 0.00
aes_control_fi 3.000s 150.477us 1 1 100.00
aes_cipher_fi 2.000s 51.531us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 312.705us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 312.705us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 312.705us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 312.705us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 110.897us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1616.172us 1 1 100.00
aes_tl_intg_err 3.000s 371.114us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 371.114us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 7.000s 10062.646us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 312.705us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 312.705us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 3.000s 74.120us 1 1 100.00
aes_stress 2.000s 114.717us 1 1 100.00
aes_alert_reset 7.000s 10062.646us 0 1 0.00
aes_core_fi 2.000s 117.264us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 57.414us 1 1 100.00
aes_config_error 2.000s 90.206us 1 1 100.00
aes_stress 2.000s 114.717us 1 1 100.00
aes_core_fi 2.000s 117.264us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 312.705us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 83.104us 1 1 100.00
aes_stress 2.000s 114.717us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 114.717us 1 1 100.00
aes_sideload 3.000s 143.049us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 83.104us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 83.104us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 83.104us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 83.104us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 83.104us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 114.717us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 114.717us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 11.000s 10047.233us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 11.000s 10047.233us 0 1 0.00
aes_control_fi 3.000s 150.477us 1 1 100.00
aes_cipher_fi 2.000s 51.531us 1 1 100.00
aes_ctr_fi 2.000s 81.446us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 11.000s 10047.233us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 11.000s 10047.233us 0 1 0.00
aes_control_fi 3.000s 150.477us 1 1 100.00
aes_cipher_fi 2.000s 51.531us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 51.531us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 11.000s 10047.233us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 11.000s 10047.233us 0 1 0.00
aes_control_fi 3.000s 150.477us 1 1 100.00
aes_ctr_fi 2.000s 81.446us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 11.000s 10047.233us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 11.000s 10047.233us 0 1 0.00
aes_control_fi 3.000s 150.477us 1 1 100.00
aes_cipher_fi 2.000s 51.531us 1 1 100.00
aes_ctr_fi 2.000s 81.446us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 7.000s 10062.646us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 11.000s 10047.233us 0 1 0.00
aes_control_fi 3.000s 150.477us 1 1 100.00
aes_cipher_fi 2.000s 51.531us 1 1 100.00
aes_ctr_fi 2.000s 81.446us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 11.000s 10047.233us 0 1 0.00
aes_control_fi 3.000s 150.477us 1 1 100.00
aes_cipher_fi 2.000s 51.531us 1 1 100.00
aes_ctr_fi 2.000s 81.446us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 11.000s 10047.233us 0 1 0.00
aes_control_fi 3.000s 150.477us 1 1 100.00
aes_ctr_fi 2.000s 81.446us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 11.000s 10047.233us 0 1 0.00
aes_ghash_fi 2.000s 50.053us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 11.000s 10047.233us 0 1 0.00
aes_control_fi 3.000s 150.477us 1 1 100.00
aes_cipher_fi 2.000s 51.531us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 10.000s 331.992us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 25745731314500387813240316352789447600110737174523771631729139071273712831962 1853
UVM_INFO @ 10062646147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 41965007623593391751482982247310667908997464120077976983431544589093469734769 26883
UVM_INFO @ 10141834807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 35062741103810749260890311351344007819281095224366873139750693013199677445450 3681
UVM_INFO @ 10047232651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:75) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 61084324081817489960666333274305464933041687963391035375189996433202516878847 235
UVM_INFO @ 331992356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---