Simulation Results: chip

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.79 %
  • code
  • 85.28 %
  • assert
  • 97.37 %
  • func
  • 32.72 %
  • line
  • 94.51 %
  • branch
  • 94.32 %
  • cond
  • 89.14 %
  • toggle
  • 91.30 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
76.98%
V2S
100.00%
V3
65.38%
unmapped
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 174.990s 2898.277us 1 1 100.00
chip_sw_example_rom 83.850s 2528.266us 1 1 100.00
chip_sw_example_manufacturer 165.860s 3062.302us 1 1 100.00
chip_sw_example_concurrency 159.360s 2658.863us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 149.280s 4906.488us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 272.430s 4496.681us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 406.770s 6954.963us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4270.840s 27741.026us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 48.100s 2100.413us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4270.840s 27741.026us 1 1 100.00
chip_csr_rw 272.430s 4496.681us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 9.440s 169.174us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 280.030s 4112.806us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 280.030s 4112.806us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 280.030s 4112.806us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 369.540s 4656.748us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 369.540s 4656.748us 1 1 100.00
chip_sw_uart_tx_rx_idx1 382.680s 3991.324us 1 1 100.00
chip_sw_uart_tx_rx_idx2 308.900s 4094.169us 1 1 100.00
chip_sw_uart_tx_rx_idx3 414.210s 4770.686us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 908.130s 7922.298us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 278.940s 3796.931us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 653.800s 9085.585us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 241.230s 4954.262us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 241.230s 4954.262us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 162.400s 2722.252us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 138.220s 3686.969us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 165.880s 3218.459us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 84.260s 2638.802us 1 1 100.00
chip_tap_straps_testunlock0 181.640s 4219.051us 1 1 100.00
chip_tap_straps_rma 215.590s 4872.892us 1 1 100.00
chip_tap_straps_prod 87.710s 3440.719us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 157.990s 3533.201us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 768.450s 10105.309us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 502.160s 5895.485us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 502.160s 5895.485us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 614.510s 7475.700us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1117.770s 11146.914us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 379.500s 4418.187us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 596.190s 5319.810us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3437.890s 19328.948us 1 1 100.00
chip_sw_aes_enc_jitter_en 146.390s 2382.490us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 709.400s 7395.937us 1 1 100.00
chip_sw_hmac_enc_jitter_en 149.060s 2831.923us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 960.760s 9400.585us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 194.150s 3428.977us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 314.280s 5303.823us 1 1 100.00
chip_sw_clkmgr_jitter 168.600s 3365.271us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 169.090s 2811.722us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 590.370s 7533.772us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 295.370s 5369.186us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 149.230s 3331.480us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 295.370s 5369.186us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 134.140s 2457.714us 1 1 100.00
chip_sw_aes_smoketest 220.630s 3686.720us 1 1 100.00
chip_sw_aon_timer_smoketest 179.530s 2830.937us 1 1 100.00
chip_sw_clkmgr_smoketest 175.250s 3435.232us 1 1 100.00
chip_sw_csrng_smoketest 178.440s 3248.487us 1 1 100.00
chip_sw_entropy_src_smoketest 830.430s 7296.623us 1 1 100.00
chip_sw_gpio_smoketest 229.870s 3049.943us 1 1 100.00
chip_sw_hmac_smoketest 210.300s 3200.294us 1 1 100.00
chip_sw_kmac_smoketest 197.690s 3342.154us 1 1 100.00
chip_sw_otbn_smoketest 1336.360s 10570.628us 1 1 100.00
chip_sw_pwrmgr_smoketest 289.800s 5922.809us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 243.870s 5239.200us 1 1 100.00
chip_sw_rv_plic_smoketest 149.740s 2433.350us 1 1 100.00
chip_sw_rv_timer_smoketest 195.460s 3209.093us 1 1 100.00
chip_sw_rstmgr_smoketest 180.910s 3104.264us 1 1 100.00
chip_sw_sram_ctrl_smoketest 155.430s 3420.163us 1 1 100.00
chip_sw_uart_smoketest 121.360s 2319.470us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 126.580s 2701.549us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 346.110s 5150.969us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 8153.320s 63794.456us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2558.420s 15291.107us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 60.075s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 247.760s 3891.088us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 191.700s 3787.500us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6915.700s 54643.314us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7331.530s 57896.558us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 82.040s 2681.970us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 82.040s 2681.970us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4270.840s 27741.026us 1 1 100.00
chip_same_csr_outstanding 1026.920s 15437.967us 1 1 100.00
chip_csr_hw_reset 149.280s 4906.488us 1 1 100.00
chip_csr_rw 272.430s 4496.681us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4270.840s 27741.026us 1 1 100.00
chip_same_csr_outstanding 1026.920s 15437.967us 1 1 100.00
chip_csr_hw_reset 149.280s 4906.488us 1 1 100.00
chip_csr_rw 272.430s 4496.681us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 60.420s 2268.987us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.010s 44.193us 1 1 100.00
xbar_smoke_large_delays 29.570s 4721.223us 1 1 100.00
xbar_smoke_slow_rsp 47.860s 5328.999us 1 1 100.00
xbar_random_zero_delays 12.500s 171.415us 1 1 100.00
xbar_random_large_delays 193.800s 31722.355us 1 1 100.00
xbar_random_slow_rsp 131.810s 14553.447us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 13.160s 370.233us 1 1 100.00
xbar_error_and_unmapped_addr 35.030s 1210.433us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 52.020s 1992.583us 1 1 100.00
xbar_error_and_unmapped_addr 35.030s 1210.433us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 20.270s 354.105us 1 1 100.00
xbar_access_same_device_slow_rsp 187.420s 21102.420us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 24.020s 482.622us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 212.470s 9389.540us 1 1 100.00
xbar_stress_all_with_error 112.940s 2427.289us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 25.610s 53.306us 1 1 100.00
xbar_stress_all_with_reset_error 207.200s 2471.027us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2558.420s 15291.107us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2360.470s 25760.539us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2788.000s 18401.888us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 67.166s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 63.179s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 157.839s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 56.515s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 30.974s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 67.814s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 130.256s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 61.611s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 64.113s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 60.333s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 169.048s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 111.407s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 85.362s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 94.604s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 9.072s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 15.260s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 14.910s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 14.930s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 14.780s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 14.780s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 15.110s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 14.950s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 14.960s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 15.020s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 15.000s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 14.930s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 14.780s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 15.060s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 15.100s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 14.990s 10.280us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 211.678s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 108.783s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 109.276s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 181.686s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 159.707s 0.000us 0 1 0.00
rom_e2e_keymgr_init 0 3 0.00
rom_e2e_keymgr_init_rom_ext_meas 2654.720s 16976.613us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 2728.240s 16374.553us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 2737.460s 15507.426us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3118.280s 17530.892us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2989.840s 35081.587us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2989.840s 35081.587us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 173.230s 3347.378us 1 1 100.00
chip_sw_aes_enc_jitter_en 146.390s 2382.490us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 144.020s 2353.058us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 179.720s 3582.523us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1565.670s 12166.158us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 137.600s 2371.077us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 361.340s 5679.019us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 417.750s 5585.737us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 571.020s 5409.202us 1 1 100.00
chip_plic_all_irqs_10 269.040s 3892.814us 1 1 100.00
chip_plic_all_irqs_20 346.810s 4231.545us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 205.180s 4205.381us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1151.220s 12507.287us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 320.540s 5139.981us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 108.110s 2826.747us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1016.840s 9806.766us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1006.670s 9315.887us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 782.280s 8624.425us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8854.800s 255447.039us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 273.070s 4253.708us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 289.800s 5922.809us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 273.070s 4253.708us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 449.450s 8544.252us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 449.450s 8544.252us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 275.480s 6195.401us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 342.660s 5900.877us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 615.750s 6396.833us 1 1 100.00
chip_sw_aes_idle 179.720s 3582.523us 1 1 100.00
chip_sw_hmac_enc_idle 186.690s 3104.944us 1 1 100.00
chip_sw_kmac_idle 147.760s 2823.539us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 244.620s 3750.290us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 270.890s 3717.617us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 244.970s 4827.807us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 312.430s 4401.943us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 803.270s 9636.314us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 344.330s 3954.506us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 388.190s 4958.625us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 355.580s 4175.634us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 394.750s 4885.801us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 379.970s 4352.488us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 393.900s 5331.683us 1 1 100.00
chip_sw_ast_clk_outputs 614.510s 7475.700us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 392.470s 6667.928us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 355.580s 4175.634us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 394.750s 4885.801us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 379.500s 4418.187us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 596.190s 5319.810us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3437.890s 19328.948us 1 1 100.00
chip_sw_aes_enc_jitter_en 146.390s 2382.490us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 709.400s 7395.937us 1 1 100.00
chip_sw_hmac_enc_jitter_en 149.060s 2831.923us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 960.760s 9400.585us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 194.150s 3428.977us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 314.280s 5303.823us 1 1 100.00
chip_sw_clkmgr_jitter 168.600s 3365.271us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 162.980s 3452.842us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 403.250s 5029.188us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 678.160s 7161.834us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3519.190s 25074.954us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 145.450s 3113.612us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 174.330s 3506.742us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1132.010s 11616.329us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 184.340s 3263.835us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 348.260s 4993.113us 1 1 100.00
chip_sw_flash_init_reduced_freq 1045.620s 22224.993us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 11375.180s 131192.545us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 614.510s 7475.700us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 382.610s 4728.346us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 229.420s 3216.297us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 417.750s 5585.737us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1016.840s 9806.766us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1900.920s 24234.275us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 135.720s 2955.458us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 440.840s 7833.712us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 153.300s 2983.555us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 1619.220s 12828.086us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 145.220s 3119.696us 1 1 100.00
chip_sw_edn_entropy_reqs 887.480s 7915.228us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 145.220s 3119.696us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1900.920s 24234.275us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 150.700s 2757.560us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1500.920s 24101.489us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 635.980s 5354.910us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 596.190s 5319.810us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 306.290s 4415.251us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 379.500s 4418.187us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3148.990s 43558.129us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1500.920s 24101.489us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 213.700s 3715.626us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1584.360s 11963.055us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 132.620s 3283.684us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3148.990s 43558.129us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 132.620s 3283.684us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 132.620s 3283.684us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 132.620s 3283.684us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 132.620s 3283.684us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 417.750s 5585.737us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 274.580s 9864.271us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 495.890s 5039.794us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 348.060s 4815.515us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 348.060s 4815.515us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 151.430s 3158.324us 1 1 100.00
chip_sw_hmac_enc_jitter_en 149.060s 2831.923us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 186.690s 3104.944us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1049.120s 7747.095us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 701.060s 5923.952us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 297.650s 4514.298us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 394.860s 5418.030us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 426.070s 4914.695us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 291.290s 4182.353us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1584.360s 11963.055us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 960.760s 9400.585us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1153.060s 9291.348us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1565.670s 12166.158us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2674.640s 16172.194us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 155.330s 2668.113us 1 1 100.00
chip_sw_kmac_mode_kmac 195.310s 3497.276us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 194.150s 3428.977us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1584.360s 11963.055us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 563.660s 11628.101us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 187.580s 3682.065us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1518.430s 10504.937us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 147.760s 2823.539us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 361.340s 5679.019us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 84.260s 2638.802us 1 1 100.00
chip_tap_straps_rma 215.590s 4872.892us 1 1 100.00
chip_tap_straps_prod 87.710s 3440.719us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 142.810s 3223.387us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 563.660s 11628.101us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 563.660s 11628.101us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 563.660s 11628.101us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1607.100s 11813.107us 1 1 100.00
chip_sw_lc_ctrl_broadcast 18 22 81.82
chip_sw_flash_ctrl_lc_rw_en 132.620s 3283.684us 0 1 0.00
chip_sw_flash_rma_unlocked 3148.990s 43558.129us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 192.830s 3338.563us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 434.440s 7063.602us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 573.860s 6866.845us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 540.410s 6076.229us 0 1 0.00
chip_sw_lc_ctrl_transition 563.660s 11628.101us 1 1 100.00
chip_sw_keymgr_key_derivation 1584.360s 11963.055us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 424.790s 8967.849us 1 1 100.00
chip_sw_sram_ctrl_execution_main 515.600s 8003.380us 0 1 0.00
chip_prim_tl_access 274.580s 9864.271us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 392.470s 6667.928us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 344.330s 3954.506us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 388.190s 4958.625us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 355.580s 4175.634us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 394.750s 4885.801us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 379.970s 4352.488us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 393.900s 5331.683us 1 1 100.00
chip_tap_straps_dev 84.260s 2638.802us 1 1 100.00
chip_tap_straps_rma 215.590s 4872.892us 1 1 100.00
chip_tap_straps_prod 87.710s 3440.719us 1 1 100.00
chip_rv_dm_lc_disabled 122.090s 4401.945us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 150.820s 2926.803us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 81.900s 2879.980us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 78.550s 3301.118us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 145.010s 3129.181us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1814.160s 27844.326us 1 1 100.00
chip_rv_dm_lc_disabled 122.090s 4401.945us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 435.700s 8521.436us 0 1 0.00
chip_sw_lc_walkthrough_prod 459.110s 9152.983us 0 1 0.00
chip_sw_lc_walkthrough_prodend 641.450s 9713.861us 1 1 100.00
chip_sw_lc_walkthrough_rma 285.220s 6948.384us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1814.160s 27844.326us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 59.960s 2551.654us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 50.580s 1872.676us 1 1 100.00
rom_volatile_raw_unlock 59.598s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3254.350s 17354.828us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3437.890s 19328.948us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 615.750s 6396.833us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 615.750s 6396.833us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 615.750s 6396.833us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 275.130s 3860.835us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 563.660s 11628.101us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1500.920s 24101.489us 1 1 100.00
chip_sw_otbn_mem_scramble 275.130s 3860.835us 1 1 100.00
chip_sw_keymgr_key_derivation 1584.360s 11963.055us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 350.370s 4396.544us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 161.020s 3121.837us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1500.920s 24101.489us 1 1 100.00
chip_sw_otbn_mem_scramble 275.130s 3860.835us 1 1 100.00
chip_sw_keymgr_key_derivation 1584.360s 11963.055us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 350.370s 4396.544us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 161.020s 3121.837us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 563.660s 11628.101us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 308.920s 4295.671us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 142.810s 3223.387us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 192.830s 3338.563us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 434.440s 7063.602us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 573.860s 6866.845us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 540.410s 6076.229us 0 1 0.00
chip_sw_lc_ctrl_transition 563.660s 11628.101us 1 1 100.00
chip_prim_tl_access 274.580s 9864.271us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 274.580s 9864.271us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 812.730s 7911.537us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 146.660s 5301.904us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 777.790s 24871.789us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 260.130s 7362.789us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 380.530s 7919.184us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 451.710s 7897.732us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1218.690s 23330.854us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 356.520s 9804.110us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 449.450s 8544.252us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 774.410s 11969.434us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 441.960s 6439.537us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 146.660s 5301.904us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 277.870s 4210.389us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 214.470s 5043.556us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 263.940s 6376.995us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 182.100s 3521.944us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1749.200s 22154.521us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 692.770s 7920.440us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 866.340s 11933.143us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1829.980s 25722.485us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 168.180s 3512.752us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 417.750s 5585.737us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 424.790s 8967.849us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 424.790s 8967.849us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 866.340s 11933.143us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1749.200s 22154.521us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 441.960s 6439.537us 1 1 100.00
chip_sw_pwrmgr_smoketest 289.800s 5922.809us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 221.200s 3922.017us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 384.210s 6789.319us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 260.200s 4280.950us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1151.220s 12507.287us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 161.550s 2665.829us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 417.750s 5585.737us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1006.670s 9315.887us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 472.700s 5107.025us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 461.910s 5367.542us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 159.760s 3052.109us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 161.020s 3121.837us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 384.210s 6789.319us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 384.210s 6789.319us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1444.330s 18591.319us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 878.990s 13682.972us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 221.200s 3922.017us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 166.280s 3407.091us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 312.630s 6704.941us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 215.590s 4872.892us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 122.090s 4401.945us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 571.020s 5409.202us 1 1 100.00
chip_plic_all_irqs_10 269.040s 3892.814us 1 1 100.00
chip_plic_all_irqs_20 346.810s 4231.545us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 165.690s 2966.202us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 138.320s 2739.559us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2558.420s 15291.107us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 463.240s 7390.868us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 178.550s 2793.506us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 192.540s 3834.164us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 210.630s 2978.381us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 350.370s 4396.544us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 314.280s 5303.823us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 501.210s 8646.230us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 350.540s 7341.220us 1 1 100.00
chip_sw_sram_execution 0 1 0.00
chip_sw_sram_ctrl_execution_main 515.600s 8003.380us 0 1 0.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 417.750s 5585.737us 1 1 100.00
chip_sw_data_integrity_escalation 502.160s 5895.485us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 692.770s 7920.440us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1059.430s 22706.044us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 190.620s 3401.411us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 241.230s 3689.945us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 360.290s 5051.673us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1059.430s 22706.044us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1059.430s 22706.044us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2208.900s 20849.376us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2208.900s 20849.376us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 273.670s 5614.977us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2989.840s 35081.587us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 124.520s 2990.601us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 139.310s 2662.858us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 279.400s 3991.603us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 276.860s 4278.223us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 959.930s 9096.741us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5100.180s 32195.898us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1810.270s 12517.455us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 160.580s 3347.084us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 160.630s 2860.968us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 61.520s 2968.691us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 10014.310s 71257.916us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 828.400s 6705.070us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 115.420s 3675.581us 0 1 0.00
rom_e2e_jtag_debug_dev 117.170s 4653.732us 0 1 0.00
rom_e2e_jtag_debug_rma 113.910s 3803.422us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 62.680s 2523.755us 0 1 0.00
rom_e2e_jtag_inject_dev 43.580s 2477.040us 0 1 0.00
rom_e2e_jtag_inject_rma 52.980s 1918.494us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 55.755s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 300.270s 4060.023us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 296.930s 3199.646us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 847.690s 5902.604us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1222.840s 9223.027us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 270.640s 2870.739us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 653.200s 5486.616us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 156.070s 2913.408us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 200.700s 3560.372us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 219.140s 5241.608us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 341.830s 4378.158us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 866.340s 11933.143us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 115.420s 3675.581us 0 1 0.00
rom_e2e_jtag_debug_dev 117.170s 4653.732us 0 1 0.00
rom_e2e_jtag_debug_rma 113.910s 3803.422us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 342.210s 5189.880us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 417.750s 5585.737us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5669.080s 38154.298us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5669.080s 38154.298us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 168.880s 3494.761us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 369.540s 4656.748us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2871.760s 19274.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 10 70.00
chip_sival_flash_info_access 185.780s 2869.856us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 361.110s 5831.266us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 4.450s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 169.630s 2805.730us 1 1 100.00
chip_sw_otp_ctrl_descrambling 204.500s 3035.603us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 253.550s 3853.310us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 10.738s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 232.090s 3045.121us 1 1 100.00
ate_bootstrap_flash_erase 6208.480s 45601.795us 1 1 100.00
ate_bootstrap_disjoint 9616.980s 84614.436us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 33114180956268776341479944493001734774104963623435325959906833430591542594209 320
UVM_INFO @ 2793.506390 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 72158896136814437615460554624864081561797714322198869822187979586995644294975 309
UVM_INFO @ 3283.684479 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 16102424230635470556097141989047487309262274181124344306552709586176122747777 342
UVM_INFO @ 6076.229345 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 112642830354529431372910394881611896830489590235851007600155260757796822739592 316
UVM_ERROR @ 3560.372312 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3560.372312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 54023498351396076146635229278457236534790906923502017892522895107386585707675 312
UVM_ERROR @ 2955.458472 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2955.458472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 56749593269570554425695106043694939894041892072694846659427783659974949004565 287
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 89287980449566112678444880875792848870237341267254500598844149195630637973701 374
UVM_INFO @ 8521.436262 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 79157716895265054352154034568310496373333275180818915494586161885054771476526 369
UVM_INFO @ 9152.983130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 17451208841796184099051645066702118780413901535793485463579696718559075812869 346
UVM_INFO @ 6948.384080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'
chip_sw_pwrmgr_full_aon_reset 16020092893116698780221348068401755586188357822936869908482094652014246044382 318
UVM_ERROR @ 5301.903793 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 5301.903793 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sram_ctrl_execution_main 17055423110557103553764073367385902009295660775796870838520933805348834633591 341
UVM_ERROR @ 8003.380000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 8003.380000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 53824690680128091209647595583942132766066977577123658792902297907485602767496 332
UVM_ERROR @ 9804.110000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9804.110000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 19173810984829675933475340544893983462108413815397868014079282375846608966786 325
UVM_ERROR @ 7919.184000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7919.184000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'
chip_sw_pwrmgr_sleep_power_glitch_reset 80638403462761868257696493438467205952322403348610475128938794232004603189775 313
UVM_ERROR @ 3521.943660 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3521.943660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 61713980381199851033370425964627736226233809337125211575666789350791482027676 320
UVM_ERROR @ 5043.555685 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 5043.555685 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 12673434182138208201669053377248944547310477093781082534751309190210480037618 337
UVM_INFO @ 35081.586969 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:397)] CHECK-fail: Expect alert *!
chip_sw_alert_test 112803736046746963378851597668986705206251374536045063051183400625207795347787 312
UVM_INFO @ 2371.077018 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 4511016109538420171627250960738162406294977622850107709889734942638770361140 313
UVM_INFO @ 2826.747225 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
chip_sw_alert_handler_lpg_sleep_mode_pings 111150066187696622467689537979330257941835312223538507684671449588819598077850 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 34139790644622624985970183621915056227969989788308176525688638889079662709051 217
TL item was: req: (cip_tl_seq_item@32481) { a_addr: 'h1055c a_data: 'hc1baef6d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h22 a_opcode: 'h4 a_user: 'h18681 d_param: 'h0 d_source: 'h22 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2681.970071 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 27947134177155921373108023107325125231885405984122935222024574550735597255937 224
TL item was: req: (cip_tl_seq_item@31465) { a_addr: 'h105dc a_data: 'hc00c1871 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h17 a_opcode: 'h4 a_user: 'h1b60d d_param: 'h0 d_source: 'h17 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2100.412720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 89769635419035317527752662242364010627263010800506009065920074067073541624825 343
UVM_INFO @ 4060.023076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()
chip_sw_pwrmgr_lowpower_cancel 99256199783765488181486456743101998121544962966067171743966510176398169903486 317
UVM_INFO @ 3853.309645 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
chip_sw_pwrmgr_sleep_wake_5_bug 89842192967305892481227526361161152086659044462347750673382844864808894163477 None
---- STDERR ----
Another command (pid=2071315) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=2072738) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 14753133010247325630796684591938447030027279925751946869771953047497322388523 None
Another command (pid=300245) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=297789) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=357441) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 13980690916636028067148271749145490288752022855866818015863507918200248260205 None
Another command (pid=378052) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=321402) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=279504) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 62398835166039245575637977221236297637867209046930184653331221522106832536028 None
Another command (pid=636405) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=520102) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=608878) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 71284157758090094520881205584089406074239584575747099836765967111831686076422 None
---- STDERR ----
Another command (pid=361417) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 92086104801149479514494106958328522366725066796267767854055764055017630797930 None
Another command (pid=309376) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=321402) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=346612) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 61514818418910494276298403810583522857097215601351105089593920251484431156370 None
Another command (pid=300245) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=297789) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=345331) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 89958390685247812523172464544198960361171210131691590880836901919548324408417 None
Another command (pid=559356) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=534887) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=468791) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 78301759241274557104215551110529893957978118556673232183588963725995921680330 None
---- STDERR ----
Another command (pid=361417) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=308589) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 23470034864203497752911725220645306691568036211629064036680873694348489192556 None
Another command (pid=358763) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=276944) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=452466) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 39949935662890108107956408912474533607677138909403205411971889668276475884538 None
---- STDERR ----
Another command (pid=361417) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 30197653769090497744925756879027092187294506567649266195496749209618386357112 None
Another command (pid=520869) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=479536) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=464573) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 79087738733982227491424699110233685100930739544776080735607215865822039993462 None
Another command (pid=462791) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=471959) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=465391) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 48708519315646935089359449493660144200969390659382236801195049459394445076149 None
Another command (pid=447782) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=296891) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=454519) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 26577899152631552730996986106172597492073683134858013621515519282785715743030 None
Another command (pid=491228) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=297385) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=489535) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 63647071636221265484026492057385924409011720399805313174532089483369474531307 None
---- STDERR ----
Another command (pid=345331) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 49802171728197924259139343692303682010466957624631537494551390494055653237528 None
Another command (pid=609872) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=611355) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=612793) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 103124212419194696497490493336058737779460335459430694149565775023164027737504 None
Another command (pid=357441) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=294991) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=361417) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 30301253360249479488220618694902750590638419761688080516363589301225002874969 None
Another command (pid=361417) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=308589) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=445567) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 69963037837838956155626242609573082267858359047332850430283409045833140812362 None
Another command (pid=458170) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=596665) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=600587) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 85712511989705156020297243496845012707645094279331003948556741492890002619550 None
Another command (pid=534887) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=468791) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=510112) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 8835283751021950796832293326599598609262223083983715334978793181005314069226 None
Another command (pid=305089) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=292495) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=297789) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 106392945098926084152103578417239705094420060098012782016870380794537725853880 None
Another command (pid=292495) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=297789) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=357441) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 10852445115631906208886481412080289785364685129665828326801931656149935412295 None
---- STDERR ----
Another command (pid=274357) is running. Waiting for it to complete on the server (server_pid=210369)...
Another command (pid=305089) is running. Waiting for it to complete on the server (server_pid=210369)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 34878975996377467783889788616219566284042848897839472592888313012763017994491 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 70381135702830096379166695638880056763202309760444406010536469924875913940033 324
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 77853231155434666151777949557186400781212594799650865455444181644365335513980 324
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 7263176194147354898877805581026891047740699740563097969467920254210401423193 308
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 29182525863369346068582332481289602665205968716217552803295457434193084144673 308
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 47452596403821158411619370446426721657725692725963208180835333692710461184842 308
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 285950979856114190817972409465543035841398398251104716821971219964585603668 225
UVM_INFO @ 4401.944757 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 58517592928122620458775614284519688913382145267745341289770594184249904415924 312
UVM_INFO @ 3891.088000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 40351682838475752998839421936876949944246701447888718685813155685459318853403 318
UVM_INFO @ 3787.500000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 21640755414049829690964442159843587296068532823645734225328117720487101730336 332
UVM_INFO @ 11146.914261 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 48782360401844660985696355236823658461878661892909420991990436110973029598649 367
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 29267143758085585068417101649805831552097125267921027721920743249760935459350 330
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 10342721127719574420571739417013568623845913257349530225800054407212726929445 371
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 60019195618417687448827071147888715855480229894431670708424214836479878825697 331
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_prod 64762697153903981363148690955087590022882786265346290898012579807495130830272 370
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 110993555999133139035491648394334244616342409122623696650334723032116431396445 371
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 1679414924526554853496360769074040747216436161467649614528069156066560769731 370
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 1595381513217233206650998193629717462513054732278797600812431241395931279721 331
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 26620031903283569563502987525680124804220599687492923770394738649107656273122 333
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 56941938853976054695790499490955411655524603186543299922857298497151950314362 333
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 17691100617257702003289612154627200261149894354454275495172333216125154444810 330
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 87187848743004367074511884750987265099895882563122419000878116624137594687382 333
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 15344366054097742105500163227832477383858686383331273049273897738795297519291 333
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 27679305542704678297987974854926803661498807701513146646342764467761015545048 333
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 24208492366311978422384625724828001388391562868166814176388726240824078042300 333
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds
rom_e2e_jtag_debug_dev 89650114763293817953119562182961905828208555553391889229029226442950019829185 318
UVM_INFO @ 4653.732292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_meas 80321985289827033444819441476143804576476666223691941368327977379334727425578 325
UVM_INFO @ 16976.613303 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)'
rom_e2e_keymgr_init_rom_ext_no_meas 105384255222275786419457347972485385907797576832611968617322349925649739026876 322
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 2398721783ps failed at 2398721783ps
Offending '(pend_req[h2d.a_source].pend == 0)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 2398878279ps failed at 2398878279ps
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_invalid_meas 87843494509678879915743409333828311314050288136872556646957557063728299575113 324
UVM_INFO @ 15507.425976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 32455872809421503804922612980878744126288465772147846579003207289444154697428 327
UVM_ERROR @ 5150.969464 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5150.969464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---