Simulation Results: clkmgr

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.05 %
  • code
  • 98.07 %
  • assert
  • 94.63 %
  • func
  • 86.45 %
  • line
  • 98.94 %
  • branch
  • 98.57 %
  • cond
  • 93.82 %
  • toggle
  • 99.03 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.870s 77.208us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.030s 34.216us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.010s 36.759us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.860s 506.913us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.460s 70.890us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.610s 74.817us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.010s 36.759us 1 1 100.00
clkmgr_csr_aliasing 1.460s 70.890us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.070s 33.080us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.820s 27.681us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 1.040s 25.151us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.040s 36.574us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.870s 77.208us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 9.570s 2485.105us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 3.460s 870.816us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 9.570s 2485.105us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 31.380s 10095.834us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.120s 21.087us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.820s 43.162us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.820s 43.162us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.030s 34.216us 1 1 100.00
clkmgr_csr_rw 1.010s 36.759us 1 1 100.00
clkmgr_csr_aliasing 1.460s 70.890us 1 1 100.00
clkmgr_same_csr_outstanding 0.860s 58.352us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.030s 34.216us 1 1 100.00
clkmgr_csr_rw 1.010s 36.759us 1 1 100.00
clkmgr_csr_aliasing 1.460s 70.890us 1 1 100.00
clkmgr_same_csr_outstanding 0.860s 58.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.680s 1.189us 0 1 0.00
clkmgr_tl_intg_err 1.440s 139.830us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.240s 72.768us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.240s 72.768us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.240s 72.768us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.240s 72.768us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.680s 200.094us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.440s 139.830us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 9.570s 2485.105us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 3.460s 870.816us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.240s 72.768us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.410s 263.440us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.900s 42.286us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.920s 38.399us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.290s 77.367us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 1.130s 109.429us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.010s 36.759us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.680s 1.189us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.010s 36.759us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.010s 36.759us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.680s 1.189us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.820s 495.186us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 39.630s 6888.601us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 27744197854803388714924319585490294757702360176227076283306497543042642240356 78
UVM_INFO @ 1188897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---