Simulation Results: csrng

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.54 %
  • code
  • 92.45 %
  • assert
  • 93.89 %
  • func
  • 73.27 %
  • block
  • 97.15 %
  • line
  • 97.87 %
  • branch
  • 92.84 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 67.561us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 26.000s 59.128us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 21.000s 16.458us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 40.000s 1048.034us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 26.000s 47.276us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 26.000s 80.579us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 21.000s 16.458us 1 1 100.00
csrng_csr_aliasing 26.000s 47.276us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 18.000s 299.368us 1 1 100.00
alerts 1 1 100.00
csrng_alert 33.000s 546.940us 1 1 100.00
err 1 1 100.00
csrng_err 21.000s 21.098us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 27.000s 45.670us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 27.000s 45.670us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 64.000s 2350.698us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 12.000s 40.650us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 26.000s 44.737us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 2.000s 45.070us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 2.000s 45.070us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 26.000s 59.128us 1 1 100.00
csrng_csr_rw 21.000s 16.458us 1 1 100.00
csrng_csr_aliasing 26.000s 47.276us 1 1 100.00
csrng_same_csr_outstanding 4.000s 254.175us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 26.000s 59.128us 1 1 100.00
csrng_csr_rw 21.000s 16.458us 1 1 100.00
csrng_csr_aliasing 26.000s 47.276us 1 1 100.00
csrng_same_csr_outstanding 4.000s 254.175us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 38.887us 1 1 100.00
csrng_tl_intg_err 4.000s 107.103us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 31.093us 1 1 100.00
csrng_csr_rw 21.000s 16.458us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 33.000s 546.940us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 64.000s 2350.698us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 18.000s 299.368us 1 1 100.00
csrng_err 21.000s 21.098us 1 1 100.00
csrng_sec_cm 2.000s 38.887us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 18.000s 299.368us 1 1 100.00
csrng_err 21.000s 21.098us 1 1 100.00
csrng_sec_cm 2.000s 38.887us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 18.000s 299.368us 1 1 100.00
csrng_err 21.000s 21.098us 1 1 100.00
csrng_sec_cm 2.000s 38.887us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 18.000s 299.368us 1 1 100.00
csrng_err 21.000s 21.098us 1 1 100.00
csrng_sec_cm 2.000s 38.887us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 18.000s 299.368us 1 1 100.00
csrng_err 21.000s 21.098us 1 1 100.00
csrng_sec_cm 2.000s 38.887us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 33.000s 546.940us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 18.000s 299.368us 1 1 100.00
csrng_err 21.000s 21.098us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 64.000s 2350.698us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 33.000s 546.940us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 107.103us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 18.000s 299.368us 1 1 100.00
csrng_err 21.000s 21.098us 1 1 100.00
csrng_sec_cm 2.000s 38.887us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 18.000s 299.368us 1 1 100.00
csrng_err 21.000s 21.098us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 18.000s 299.368us 1 1 100.00
csrng_err 21.000s 21.098us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 18.000s 299.368us 1 1 100.00
csrng_err 21.000s 21.098us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 18.000s 299.368us 1 1 100.00
csrng_err 21.000s 21.098us 1 1 100.00
csrng_sec_cm 2.000s 38.887us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 18.000s 299.368us 1 1 100.00
csrng_err 21.000s 21.098us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*])
csrng_cmds 44053748073702172105062952099667847929588301264783473787969927603920504130279 130
UVM_INFO @ 45669934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
csrng_stress_all_with_rand_reset 30222853298584335889761628926032095191692321900395773689956602405030042110840 None