Simulation Results: edn/edn0

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.13 %
  • code
  • 81.99 %
  • assert
  • 95.66 %
  • func
  • 80.75 %
  • line
  • 97.34 %
  • branch
  • 91.07 %
  • cond
  • 86.71 %
  • toggle
  • 85.35 %
  • FSM
  • 49.46 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.760s 63.802us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.970s 48.188us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.990s 27.807us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.920s 1043.231us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.200s 54.704us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.990s 19.311us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.990s 27.807us 1 1 100.00
edn_csr_aliasing 1.200s 54.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.470s 31.799us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.470s 31.799us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.470s 31.799us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 24.254us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.060s 51.876us 1 1 100.00
errs 1 1 100.00
edn_err 0.960s 21.687us 1 1 100.00
disable 2 2 100.00
edn_disable 0.820s 15.181us 1 1 100.00
edn_disable_auto_req_mode 1.240s 85.482us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.060s 222.977us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.800s 21.807us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.010s 195.236us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.420s 31.665us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.420s 31.665us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.970s 48.188us 1 1 100.00
edn_csr_rw 0.990s 27.807us 1 1 100.00
edn_csr_aliasing 1.200s 54.704us 1 1 100.00
edn_same_csr_outstanding 1.330s 44.841us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.970s 48.188us 1 1 100.00
edn_csr_rw 0.990s 27.807us 1 1 100.00
edn_csr_aliasing 1.200s 54.704us 1 1 100.00
edn_same_csr_outstanding 1.330s 44.841us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 10.150s 908.608us 1 1 100.00
edn_tl_intg_err 1.430s 158.382us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.950s 62.524us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.060s 51.876us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.150s 908.608us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 10.150s 908.608us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 10.150s 908.608us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 10.150s 908.608us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.060s 51.876us 1 1 100.00
edn_sec_cm 10.150s 908.608us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.060s 51.876us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.430s 158.382us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 50.940s 7727.755us 1 1 100.00