Simulation Results: edn/edn1

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.80 %
  • code
  • 82.59 %
  • assert
  • 97.14 %
  • func
  • 80.67 %
  • line
  • 97.88 %
  • branch
  • 92.64 %
  • cond
  • 90.00 %
  • toggle
  • 88.13 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.810s 21.650us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 28.576us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.890s 68.760us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.430s 1015.812us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.030s 44.310us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.930s 19.160us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.890s 68.760us 1 1 100.00
edn_csr_aliasing 1.030s 44.310us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.030s 76.183us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.030s 76.183us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.030s 76.183us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.820s 76.617us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.990s 24.371us 1 1 100.00
errs 1 1 100.00
edn_err 0.850s 41.563us 1 1 100.00
disable 2 2 100.00
edn_disable 0.920s 12.289us 1 1 100.00
edn_disable_auto_req_mode 0.970s 154.943us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.680s 305.991us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.730s 43.943us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.840s 33.480us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.910s 115.940us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.910s 115.940us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.810s 28.576us 1 1 100.00
edn_csr_rw 0.890s 68.760us 1 1 100.00
edn_csr_aliasing 1.030s 44.310us 1 1 100.00
edn_same_csr_outstanding 0.980s 20.953us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.810s 28.576us 1 1 100.00
edn_csr_rw 0.890s 68.760us 1 1 100.00
edn_csr_aliasing 1.030s 44.310us 1 1 100.00
edn_same_csr_outstanding 0.980s 20.953us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.550s 314.551us 1 1 100.00
edn_tl_intg_err 1.880s 343.339us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.780s 85.007us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.990s 24.371us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.550s 314.551us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.550s 314.551us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.550s 314.551us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.550s 314.551us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.990s 24.371us 1 1 100.00
edn_sec_cm 2.550s 314.551us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.990s 24.371us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.880s 343.339us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 73.530s 19844.320us 1 1 100.00