Simulation Results: flash_ctrl

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.60 %
  • code
  • 94.28 %
  • assert
  • 96.76 %
  • func
  • 95.76 %
  • line
  • 95.98 %
  • branch
  • 97.14 %
  • cond
  • 94.05 %
  • toggle
  • 97.83 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
98.28%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 33.960s 243.606us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 9.150s 29.257us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 15.220s 604.501us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.940s 77.362us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 62.690s 13638.639us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 19.130s 834.252us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.650s 208.240us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.940s 77.362us 1 1 100.00
flash_ctrl_csr_aliasing 19.130s 834.252us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.270s 17.815us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 8.030s 131.810us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.870s 92.393us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 31.020s 37.769us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1226.780s 125561.883us 1 1 100.00
flash_ctrl_hw_rma_reset 749.400s 210212.610us 1 1 100.00
flash_ctrl_lcmgr_intg 7.300s 76.073us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1021.120s 488528.257us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 166.540s 1424.560us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 8.990s 80.298us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1757.870s 159583.280us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 34.870s 74.483us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.780s 43.253us 1 1 100.00
flash_ctrl_rw_evict_all_en 11.890s 38.515us 1 1 100.00
flash_ctrl_re_evict 15.650s 229.154us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 123.120s 750.117us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 123.120s 750.117us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 546.520s 69467.616us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.880s 1882.897us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 393.500s 3765.881us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 405.330s 52283.692us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 300.740s 375.544us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 696.220s 433.113us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.820s 50.417us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 91.220s 1026.911us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 8.790s 31.539us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 5.720s 29.121us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 312.700s 411.306us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 54.530s 9940.939us 1 1 100.00
flash_ctrl_otp_reset 54.270s 135.859us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1226.780s 125561.883us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 147.220s 1563.419us 1 1 100.00
flash_ctrl_intr_wr 49.940s 7218.416us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 154.420s 12113.267us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 134.450s 89767.845us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 39.940s 3121.514us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 33.570s 1139.003us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.980s 61.097us 1 1 100.00
flash_ctrl_ro_derr 103.390s 2562.301us 1 1 100.00
flash_ctrl_rw_derr 171.580s 3808.267us 1 1 100.00
flash_ctrl_derr_detect 111.010s 3474.926us 1 1 100.00
flash_ctrl_integrity 504.610s 22891.048us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.200s 25.273us 1 1 100.00
flash_ctrl_ro_serr 82.580s 1951.642us 1 1 100.00
flash_ctrl_rw_serr 161.020s 6768.451us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 63.190s 2174.167us 1 1 100.00
singlebit_err_address 0 1 0.00
flash_ctrl_serr_address 0.000s 0.000us 0 1 0.00
scramble 5 5 100.00
flash_ctrl_wo 121.710s 2785.426us 1 1 100.00
flash_ctrl_write_word_sweep 12.390s 329.947us 1 1 100.00
flash_ctrl_read_word_sweep 5.800s 160.577us 1 1 100.00
flash_ctrl_ro 74.890s 509.922us 1 1 100.00
flash_ctrl_rw 434.150s 64992.540us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 26.400s 1901.755us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 615.000s 89629.227us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 78.650s 10022.161us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.830s 34.779us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 8.310s 30.310us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 15.140s 467.469us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 15.140s 467.469us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.220s 604.501us 1 1 100.00
flash_ctrl_csr_rw 7.940s 77.362us 1 1 100.00
flash_ctrl_csr_aliasing 19.130s 834.252us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.730s 224.370us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.220s 604.501us 1 1 100.00
flash_ctrl_csr_rw 7.940s 77.362us 1 1 100.00
flash_ctrl_csr_aliasing 19.130s 834.252us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.730s 224.370us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 21.900s 43.831us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 21.900s 43.831us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 21.900s 43.831us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 21.900s 43.831us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 43.420s 364.762us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1382.590s 8411.088us 1 1 100.00
flash_ctrl_tl_intg_err 364.510s 3874.773us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 364.510s 3874.773us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 364.510s 3874.773us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.500s 335.952us 1 1 100.00
flash_ctrl_wr_intg 8.850s 79.592us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 33.960s 243.606us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 54.270s 135.859us 1 1 100.00
flash_ctrl_disable 8.790s 31.539us 1 1 100.00
flash_ctrl_sec_info_access 46.190s 7605.872us 1 1 100.00
flash_ctrl_connect 5.720s 29.121us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.670s 66.156us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.940s 77.362us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 21.900s 43.831us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.940s 77.362us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 21.900s 43.831us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.940s 77.362us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 21.900s 43.831us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 8.790s 31.539us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.500s 335.952us 1 1 100.00
flash_ctrl_access_after_disable 5.550s 21.363us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.240s 27.752us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 8.790s 31.539us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.880s 1882.897us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 434.150s 64992.540us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 161.020s 6768.451us 1 1 100.00
flash_ctrl_rw_derr 171.580s 3808.267us 1 1 100.00
flash_ctrl_integrity 504.610s 22891.048us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1226.780s 125561.883us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1382.590s 8411.088us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1382.590s 8411.088us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1382.590s 8411.088us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1382.590s 8411.088us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 12.820s 889.584us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 7.180s 100.192us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.430s 32.283us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1382.590s 8411.088us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1382.590s 8411.088us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1382.590s 8411.088us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 17.930s 175.351us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 263.860s 654.588us 1 1 100.00

Error Messages

   Test seed line log context
Job killed!
flash_ctrl_serr_address 11812880788488895302464131901376340597983707649700783548650580881280614494484 None