Simulation Results: hmac

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.25 %
  • code
  • 97.89 %
  • assert
  • 96.70 %
  • func
  • 43.16 %
  • line
  • 99.64 %
  • branch
  • 99.34 %
  • cond
  • 96.35 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.930s 1461.021us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.980s 188.887us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.800s 116.786us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.300s 4099.555us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.300s 611.476us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 707.250s 369618.733us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.800s 116.786us 1 1 100.00
hmac_csr_aliasing 4.300s 611.476us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 48.460s 5546.172us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 47.320s 1107.138us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 169.490s 5301.739us 1 1 100.00
hmac_test_sha384_vectors 449.420s 12654.519us 1 1 100.00
hmac_test_sha512_vectors 397.780s 154188.116us 1 1 100.00
hmac_test_hmac256_vectors 9.830s 282.757us 1 1 100.00
hmac_test_hmac384_vectors 9.120s 309.570us 1 1 100.00
hmac_test_hmac512_vectors 9.100s 255.262us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 12.420s 3027.785us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 873.940s 6179.138us 1 1 100.00
error 1 1 100.00
hmac_error 11.640s 1766.945us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 47.810s 4534.167us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.930s 1461.021us 1 1 100.00
hmac_long_msg 48.460s 5546.172us 1 1 100.00
hmac_back_pressure 47.320s 1107.138us 1 1 100.00
hmac_datapath_stress 873.940s 6179.138us 1 1 100.00
hmac_burst_wr 12.420s 3027.785us 1 1 100.00
hmac_stress_all 410.450s 16934.681us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.930s 1461.021us 1 1 100.00
hmac_long_msg 48.460s 5546.172us 1 1 100.00
hmac_back_pressure 47.320s 1107.138us 1 1 100.00
hmac_datapath_stress 873.940s 6179.138us 1 1 100.00
hmac_wipe_secret 47.810s 4534.167us 1 1 100.00
hmac_test_sha256_vectors 169.490s 5301.739us 1 1 100.00
hmac_test_sha384_vectors 449.420s 12654.519us 1 1 100.00
hmac_test_sha512_vectors 397.780s 154188.116us 1 1 100.00
hmac_test_hmac256_vectors 9.830s 282.757us 1 1 100.00
hmac_test_hmac384_vectors 9.120s 309.570us 1 1 100.00
hmac_test_hmac512_vectors 9.100s 255.262us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.930s 1461.021us 1 1 100.00
hmac_long_msg 48.460s 5546.172us 1 1 100.00
hmac_back_pressure 47.320s 1107.138us 1 1 100.00
hmac_datapath_stress 873.940s 6179.138us 1 1 100.00
hmac_burst_wr 12.420s 3027.785us 1 1 100.00
hmac_error 11.640s 1766.945us 1 1 100.00
hmac_wipe_secret 47.810s 4534.167us 1 1 100.00
hmac_test_sha256_vectors 169.490s 5301.739us 1 1 100.00
hmac_test_sha384_vectors 449.420s 12654.519us 1 1 100.00
hmac_test_sha512_vectors 397.780s 154188.116us 1 1 100.00
hmac_test_hmac256_vectors 9.830s 282.757us 1 1 100.00
hmac_test_hmac384_vectors 9.120s 309.570us 1 1 100.00
hmac_test_hmac512_vectors 9.100s 255.262us 1 1 100.00
hmac_stress_all 410.450s 16934.681us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 410.450s 16934.681us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.600s 51.051us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.590s 46.133us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.600s 579.772us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.600s 579.772us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.980s 188.887us 1 1 100.00
hmac_csr_rw 0.800s 116.786us 1 1 100.00
hmac_csr_aliasing 4.300s 611.476us 1 1 100.00
hmac_same_csr_outstanding 1.290s 175.719us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.980s 188.887us 1 1 100.00
hmac_csr_rw 0.800s 116.786us 1 1 100.00
hmac_csr_aliasing 4.300s 611.476us 1 1 100.00
hmac_same_csr_outstanding 1.290s 175.719us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.240s 180.674us 1 1 100.00
hmac_tl_intg_err 1.900s 303.005us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.900s 303.005us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.930s 1461.021us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.980s 101.231us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 30.310s 813.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.200s 100.100us 1 1 100.00