Simulation Results: i2c

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.85 %
  • code
  • 82.11 %
  • assert
  • 96.19 %
  • func
  • 82.24 %
  • line
  • 96.75 %
  • branch
  • 92.76 %
  • cond
  • 85.53 %
  • toggle
  • 89.66 %
  • FSM
  • 45.83 %
Validation stages
V1
100.00%
V2
92.68%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 16.360s 6433.988us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 20.280s 3867.533us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.910s 60.325us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.800s 18.475us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.890s 2065.127us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.630s 74.400us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.830s 30.083us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.800s 18.475us 1 1 100.00
i2c_csr_aliasing 1.630s 74.400us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.670s 21.097us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 0.750s 104.772us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 2.870s 852.483us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.870s 92.254us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 79.960s 18607.970us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 38.760s 2189.674us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.050s 1447.403us 1 1 100.00
i2c_host_fifo_fmt_empty 4.970s 1660.679us 1 1 100.00
i2c_host_fifo_reset_rx 3.320s 760.022us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 58.900s 3106.997us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 17.760s 1537.884us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 1.410s 257.715us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 1.990s 424.944us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 130.620s 69130.299us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.630s 733.127us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 38.810s 2359.580us 1 1 100.00
i2c_target_intr_smoke 4.960s 1025.948us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.370s 256.474us 1 1 100.00
i2c_target_fifo_reset_tx 1.440s 520.800us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 634.750s 53794.093us 1 1 100.00
i2c_target_stress_rd 38.810s 2359.580us 1 1 100.00
i2c_target_intr_stress_wr 11.690s 10446.836us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.290s 1112.601us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 33.220s 1334.238us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 4.760s 4411.707us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.840s 316.561us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.640s 2959.359us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.470s 644.158us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 2.870s 852.483us 1 1 100.00
i2c_host_perf_precise 101.960s 24578.227us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 17.760s 1537.884us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 3.700s 238.278us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.960s 513.788us 1 1 100.00
i2c_target_nack_acqfull_addr 2.210s 2356.863us 1 1 100.00
i2c_target_nack_txstretch 1.990s 161.541us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 6.210s 6547.294us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 2.630s 468.637us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.670s 18.303us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.970s 17.643us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.180s 516.234us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.180s 516.234us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.910s 60.325us 1 1 100.00
i2c_csr_rw 0.800s 18.475us 1 1 100.00
i2c_csr_aliasing 1.630s 74.400us 1 1 100.00
i2c_same_csr_outstanding 0.980s 106.559us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.910s 60.325us 1 1 100.00
i2c_csr_rw 0.800s 18.475us 1 1 100.00
i2c_csr_aliasing 1.630s 74.400us 1 1 100.00
i2c_same_csr_outstanding 0.980s 106.559us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.950s 514.335us 1 1 100.00
i2c_sec_cm 1.030s 94.084us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.950s 514.335us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 7.910s 1185.255us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.840s 166.938us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 1.420s 147.917us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 35163995532081909845735422924814082746515079268993417055924302747352174793676 80
UVM_INFO @ 21097318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 42573425284368232895905123347970229338278654692215199703593858069762987428877 86
UVM_INFO @ 104772363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 2859019455032162387400228345699324592222107094970341083147092573902673267691 85
UVM_INFO @ 147917101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 18944755029469432795932839898644449942150566547254075142455527061908782450779 84
UVM_INFO @ 424944205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*])
i2c_target_unexp_stop 74445071845868846133850358142266088050440119186453141031366269527555048661654 78
UVM_INFO @ 166937922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 89367446270720022988422043636342629135691808762581401386334206596583225906583 89
UVM_INFO @ 1185254643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---