Simulation Results: keymgr

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.97 %
  • code
  • 94.33 %
  • assert
  • 97.26 %
  • func
  • 60.31 %
  • line
  • 98.72 %
  • branch
  • 97.44 %
  • cond
  • 94.08 %
  • toggle
  • 95.38 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.370s 92.867us 1 1 100.00
random 1 1 100.00
keymgr_random 5.290s 505.867us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.380s 35.482us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.310s 51.189us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 8.810s 1047.548us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 9.990s 461.450us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.950s 104.737us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.310s 51.189us 1 1 100.00
keymgr_csr_aliasing 9.990s 461.450us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 28.170s 1616.984us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.750s 277.308us 1 1 100.00
keymgr_sideload_kmac 19.480s 4137.998us 1 1 100.00
keymgr_sideload_aes 7.520s 4505.361us 1 1 100.00
keymgr_sideload_otbn 2.710s 120.441us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 2.850s 342.161us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 15.280s 1296.905us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.970s 152.925us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.890s 696.635us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 4.110s 638.165us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 5.060s 427.159us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 28.690s 2221.801us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.840s 21.864us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.770s 25.402us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.770s 212.469us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.770s 212.469us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.380s 35.482us 1 1 100.00
keymgr_csr_rw 1.310s 51.189us 1 1 100.00
keymgr_csr_aliasing 9.990s 461.450us 1 1 100.00
keymgr_same_csr_outstanding 3.160s 1258.908us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.380s 35.482us 1 1 100.00
keymgr_csr_rw 1.310s 51.189us 1 1 100.00
keymgr_csr_aliasing 9.990s 461.450us 1 1 100.00
keymgr_same_csr_outstanding 3.160s 1258.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 13.960s 2517.846us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 13.960s 2517.846us 1 1 100.00
keymgr_tl_intg_err 5.500s 237.473us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 1.410s 83.210us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 1.410s 83.210us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 1.410s 83.210us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 1.410s 83.210us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 3.990s 92.449us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 13.960s 2517.846us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 13.960s 2517.846us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 5.500s 237.473us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 1.410s 83.210us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 28.170s 1616.984us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 5.290s 505.867us 1 1 100.00
keymgr_csr_rw 1.310s 51.189us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 5.290s 505.867us 1 1 100.00
keymgr_csr_rw 1.310s 51.189us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 5.290s 505.867us 1 1 100.00
keymgr_csr_rw 1.310s 51.189us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 15.280s 1296.905us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 4.110s 638.165us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 4.110s 638.165us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 5.290s 505.867us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 3.240s 97.407us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 13.960s 2517.846us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 13.960s 2517.846us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 13.960s 2517.846us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 1.740s 319.210us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 15.280s 1296.905us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 13.960s 2517.846us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 13.960s 2517.846us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 13.960s 2517.846us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.740s 319.210us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.740s 319.210us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 13.960s 2517.846us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.740s 319.210us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 13.960s 2517.846us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 1.740s 319.210us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 9.160s 992.270us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 98751214466981531058697472087329831232570634180253320162100301602142642126665 1532
UVM_INFO @ 992269685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---