Simulation Results: kmac/unmasked

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.32 %
  • code
  • 89.15 %
  • assert
  • 97.75 %
  • func
  • 93.07 %
  • line
  • 97.27 %
  • branch
  • 95.36 %
  • cond
  • 94.47 %
  • toggle
  • 99.96 %
  • FSM
  • 58.68 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 46.040s 3820.113us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.270s 171.352us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.870s 24.641us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 11.880s 299.971us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 4.280s 935.141us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.280s 24.469us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.870s 24.641us 1 1 100.00
kmac_csr_aliasing 4.280s 935.141us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.840s 22.698us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.740s 143.574us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 377.670s 6378.629us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 304.330s 13739.184us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1669.280s 124336.282us 1 1 100.00
kmac_test_vectors_sha3_256 20.630s 581.864us 1 1 100.00
kmac_test_vectors_sha3_384 23.830s 6870.709us 1 1 100.00
kmac_test_vectors_sha3_512 14.190s 2181.885us 1 1 100.00
kmac_test_vectors_shake_128 155.000s 105709.088us 1 1 100.00
kmac_test_vectors_shake_256 204.690s 5429.896us 1 1 100.00
kmac_test_vectors_kmac 2.420s 81.196us 1 1 100.00
kmac_test_vectors_kmac_xof 1.930s 305.951us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 253.530s 4345.699us 1 1 100.00
app 1 1 100.00
kmac_app 31.060s 4432.185us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 183.110s 129996.962us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 242.530s 67915.142us 1 1 100.00
error 1 1 100.00
kmac_error 155.290s 2673.175us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 2.760s 2351.374us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 15.780s 10225.858us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 5.380s 328.540us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 11.340s 2198.665us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 3.230s 800.146us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.650s 207.508us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 45.550s 12225.337us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 1.080s 24.500us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.910s 51.831us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.230s 55.167us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.230s 55.167us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.270s 171.352us 1 1 100.00
kmac_csr_rw 0.870s 24.641us 1 1 100.00
kmac_csr_aliasing 4.280s 935.141us 1 1 100.00
kmac_same_csr_outstanding 2.770s 93.466us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.270s 171.352us 1 1 100.00
kmac_csr_rw 0.870s 24.641us 1 1 100.00
kmac_csr_aliasing 4.280s 935.141us 1 1 100.00
kmac_same_csr_outstanding 2.770s 93.466us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.960s 152.101us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.960s 152.101us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.960s 152.101us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.960s 152.101us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.880s 195.356us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 46.590s 4835.025us 1 1 100.00
kmac_tl_intg_err 4.390s 382.221us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 4.390s 382.221us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.650s 207.508us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 46.040s 3820.113us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 253.530s 4345.699us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.960s 152.101us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 46.590s 4835.025us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 46.590s 4835.025us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 46.590s 4835.025us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 46.040s 3820.113us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.650s 207.508us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 46.590s 4835.025us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 154.650s 10086.009us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 46.040s 3820.113us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 208.550s 17629.777us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7)
kmac_sideload_invalid 113724173189720654893495287067197897656937004661495632513830090138222983979232 84
UVM_INFO @ 10225858019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---