Simulation Results: lc_ctrl/volatile_unlock_disabled

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.74 %
  • code
  • 84.32 %
  • assert
  • 94.13 %
  • func
  • 93.77 %
  • line
  • 97.26 %
  • branch
  • 93.97 %
  • cond
  • 79.10 %
  • toggle
  • 86.76 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.450s 26.096us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.250s 133.705us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.140s 45.221us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.850s 355.629us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.710s 179.948us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.160s 19.452us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.140s 45.221us 1 1 100.00
lc_ctrl_csr_aliasing 1.710s 179.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.470s 53.564us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.170s 386.148us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.280s 22.568us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.310s 76.369us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.960s 355.793us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.810s 404.253us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.960s 355.793us 1 1 100.00
lc_ctrl_prog_failure 3.310s 76.369us 1 1 100.00
lc_ctrl_errors 5.810s 404.253us 1 1 100.00
lc_ctrl_security_escalation 7.530s 328.117us 1 1 100.00
lc_ctrl_jtag_state_failure 47.310s 16043.470us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.820s 231.974us 1 1 100.00
lc_ctrl_jtag_errors 29.940s 13225.842us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 8.820s 1072.898us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.990s 796.055us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.820s 231.974us 1 1 100.00
lc_ctrl_jtag_errors 29.940s 13225.842us 1 1 100.00
lc_ctrl_jtag_access 4.450s 630.702us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.940s 2591.562us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.060s 444.454us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.230s 170.663us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.270s 1006.488us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.950s 6080.668us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.340s 24.358us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.720s 242.614us 1 1 100.00
lc_ctrl_jtag_alert_test 1.740s 184.955us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.230s 124.878us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.960s 23.987us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 232.390s 11617.237us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.330s 17.845us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.460s 248.104us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.460s 248.104us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.250s 133.705us 1 1 100.00
lc_ctrl_csr_rw 1.140s 45.221us 1 1 100.00
lc_ctrl_csr_aliasing 1.710s 179.948us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.650s 84.868us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.250s 133.705us 1 1 100.00
lc_ctrl_csr_rw 1.140s 45.221us 1 1 100.00
lc_ctrl_csr_aliasing 1.710s 179.948us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.650s 84.868us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.550s 236.773us 1 1 100.00
lc_ctrl_tl_intg_err 1.370s 54.942us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.370s 54.942us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.170s 386.148us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.960s 355.793us 1 1 100.00
lc_ctrl_sec_cm 7.550s 236.773us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.960s 355.793us 1 1 100.00
lc_ctrl_sec_cm 7.550s 236.773us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.960s 355.793us 1 1 100.00
lc_ctrl_sec_cm 7.550s 236.773us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.960s 355.793us 1 1 100.00
lc_ctrl_sec_cm 7.550s 236.773us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.960s 355.793us 1 1 100.00
lc_ctrl_sec_cm 7.550s 236.773us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.960s 355.793us 1 1 100.00
lc_ctrl_sec_cm 7.550s 236.773us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.960s 355.793us 1 1 100.00
lc_ctrl_sec_cm 7.550s 236.773us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.960s 355.793us 1 1 100.00
lc_ctrl_sec_cm 7.550s 236.773us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.530s 328.117us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.470s 53.564us 1 1 100.00
lc_ctrl_jtag_state_post_trans 12.990s 796.055us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.650s 3471.797us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.650s 3471.797us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.590s 598.679us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.250s 321.427us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.250s 321.427us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 21.390s 2383.065us 1 1 100.00