Simulation Results: lc_ctrl/volatile_unlock_enabled

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.63 %
  • code
  • 84.51 %
  • assert
  • 94.13 %
  • func
  • 93.24 %
  • line
  • 97.15 %
  • branch
  • 93.62 %
  • cond
  • 79.42 %
  • toggle
  • 88.79 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.700s 40.013us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.960s 67.741us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.950s 17.941us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.200s 44.742us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.410s 55.783us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.160s 76.709us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.950s 17.941us 1 1 100.00
lc_ctrl_csr_aliasing 1.410s 55.783us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 7.220s 126.261us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.170s 420.860us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.820s 15.995us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.510s 38.169us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.420s 313.861us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.040s 342.825us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.420s 313.861us 1 1 100.00
lc_ctrl_prog_failure 1.510s 38.169us 1 1 100.00
lc_ctrl_errors 5.040s 342.825us 1 1 100.00
lc_ctrl_security_escalation 5.190s 308.331us 1 1 100.00
lc_ctrl_jtag_state_failure 26.770s 5275.404us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.720s 219.622us 1 1 100.00
lc_ctrl_jtag_errors 20.730s 1756.924us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.090s 94.165us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.100s 2123.261us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.720s 219.622us 1 1 100.00
lc_ctrl_jtag_errors 20.730s 1756.924us 1 1 100.00
lc_ctrl_jtag_access 6.980s 5098.848us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.480s 969.924us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.230s 630.467us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.270s 306.560us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.720s 745.722us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.940s 563.871us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.260s 58.613us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.950s 49.751us 1 1 100.00
lc_ctrl_jtag_alert_test 1.290s 71.196us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.320s 1431.054us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.180s 49.966us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 107.920s 193240.528us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.920s 30.354us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.540s 78.973us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.540s 78.973us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 67.741us 1 1 100.00
lc_ctrl_csr_rw 0.950s 17.941us 1 1 100.00
lc_ctrl_csr_aliasing 1.410s 55.783us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.950s 155.934us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 67.741us 1 1 100.00
lc_ctrl_csr_rw 0.950s 17.941us 1 1 100.00
lc_ctrl_csr_aliasing 1.410s 55.783us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.950s 155.934us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.310s 255.307us 1 1 100.00
lc_ctrl_tl_intg_err 2.100s 121.586us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.100s 121.586us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.170s 420.860us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.420s 313.861us 1 1 100.00
lc_ctrl_sec_cm 5.310s 255.307us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.420s 313.861us 1 1 100.00
lc_ctrl_sec_cm 5.310s 255.307us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.420s 313.861us 1 1 100.00
lc_ctrl_sec_cm 5.310s 255.307us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.420s 313.861us 1 1 100.00
lc_ctrl_sec_cm 5.310s 255.307us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.420s 313.861us 1 1 100.00
lc_ctrl_sec_cm 5.310s 255.307us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.420s 313.861us 1 1 100.00
lc_ctrl_sec_cm 5.310s 255.307us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.420s 313.861us 1 1 100.00
lc_ctrl_sec_cm 5.310s 255.307us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.420s 313.861us 1 1 100.00
lc_ctrl_sec_cm 5.310s 255.307us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.190s 308.331us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 7.220s 126.261us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.100s 2123.261us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 11.220s 562.917us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 11.220s 562.917us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.470s 1958.542us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.460s 4118.385us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.460s 4118.385us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 17.980s 1935.272us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 103817141558361692763999173195895301869797014746657843031210294642013610731716 166
UVM_INFO @ 1935271614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---