Simulation Results: otbn

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.09 %
  • code
  • 95.27 %
  • assert
  • 89.99 %
  • func
  • 97.03 %
  • block
  • 99.37 %
  • line
  • 99.57 %
  • branch
  • 91.94 %
  • toggle
  • 92.11 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
92.86%
V2S
92.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 51.113us 1 1 100.00
single_binary 1 1 100.00
otbn_single 6.000s 71.399us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 30.306us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 16.125us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 125.677us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 3.000s 49.765us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 408.051us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 16.125us 1 1 100.00
otbn_csr_aliasing 3.000s 49.765us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 32.000s 1005.109us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 50.000s 1013.603us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 52.000s 313.922us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 49.000s 539.939us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 107.000s 803.204us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 66.000s 1466.957us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 7.000s 92.521us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 4.000s 40.851us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 5.000s 34.084us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 74.176us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 47.825us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 127.772us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 127.772us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 30.306us 1 1 100.00
otbn_csr_rw 3.000s 16.125us 1 1 100.00
otbn_csr_aliasing 3.000s 49.765us 1 1 100.00
otbn_same_csr_outstanding 3.000s 14.441us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 30.306us 1 1 100.00
otbn_csr_rw 3.000s 16.125us 1 1 100.00
otbn_csr_aliasing 3.000s 49.765us 1 1 100.00
otbn_same_csr_outstanding 3.000s 14.441us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 5.000s 79.691us 1 1 100.00
otbn_dmem_err 7.000s 16.719us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 8.000s 116.192us 1 1 100.00
otbn_controller_ispr_rdata_err 7.000s 101.832us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 113.441us 1 1 100.00
otbn_urnd_err 4.000s 23.585us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 16.346us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 4.000s 30.522us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 10.000s 49.684us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 166.000s 960.915us 1 1 100.00
otbn_tl_intg_err 8.000s 197.857us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 34.000s 621.814us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 166.000s 960.915us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 166.000s 960.915us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 51.113us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 7.000s 16.719us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 5.000s 79.691us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 8.000s 197.857us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 92.521us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 5.000s 79.691us 1 1 100.00
otbn_dmem_err 7.000s 16.719us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 40.851us 0 1 0.00
otbn_illegal_mem_acc 6.000s 16.346us 1 1 100.00
otbn_sec_cm 166.000s 960.915us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 166.000s 960.915us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 6.000s 71.399us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 5.000s 79.691us 1 1 100.00
otbn_dmem_err 7.000s 16.719us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 40.851us 0 1 0.00
otbn_illegal_mem_acc 6.000s 16.346us 1 1 100.00
otbn_sec_cm 166.000s 960.915us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 166.000s 960.915us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 92.521us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 5.000s 79.691us 1 1 100.00
otbn_dmem_err 7.000s 16.719us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 40.851us 0 1 0.00
otbn_illegal_mem_acc 6.000s 16.346us 1 1 100.00
otbn_sec_cm 166.000s 960.915us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 166.000s 960.915us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 6.000s 71.399us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 270.349us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 5.000s 30.030us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 27.000s 126.355us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 27.000s 126.355us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 39.514us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 166.000s 960.915us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 166.000s 960.915us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 227.056us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 166.000s 960.915us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 166.000s 960.915us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 11.000s 66.012us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 11.000s 66.012us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 9.547us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 71.399us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 71.399us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 6.000s 71.399us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 107.000s 803.204us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 6.000s 71.399us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 6.000s 71.399us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 5.000s 13.637us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 6.000s 71.399us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 166.000s 960.915us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 36.000s 215.858us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 19.893us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 111073455718619071192436692570846151606043655553139498425981876840150290383591 186
UVM_INFO @ 215857766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.u_otbn_core.u_otbn_rnd.u_xoshiro256pp.xoshiro_q cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_zero_state_err_urnd 28773252458181855522946459283965011951253555632794372360151181971598051120805 105
UVM_INFO @ 40851394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ3] name tb.dut.edn_urnd_ack cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
otbn_urnd_err 71222393153025010862289935693654074464604879298119019868339286093070276045139 103
UVM_INFO @ 23584594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---