Simulation Results: pwrmgr

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.28 %
  • code
  • 94.44 %
  • assert
  • 96.34 %
  • func
  • 95.06 %
  • line
  • 98.92 %
  • branch
  • 95.61 %
  • cond
  • 93.64 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.780s 26.608us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.760s 26.201us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.850s 19.457us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.500s 169.000us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.920s 54.546us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.240s 69.785us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.850s 19.457us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 54.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 1.160s 234.334us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 1.160s 234.334us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.920s 52.004us 1 1 100.00
pwrmgr_lowpower_invalid 0.840s 42.808us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.820s 64.799us 1 1 100.00
pwrmgr_reset_invalid 0.940s 114.406us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.820s 64.799us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.730s 67.932us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.770s 128.137us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 1.120s 112.593us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 0.770s 251.451us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.690s 18.090us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.130s 52.197us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.130s 52.197us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.760s 26.201us 1 1 100.00
pwrmgr_csr_rw 0.850s 19.457us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 54.546us 1 1 100.00
pwrmgr_same_csr_outstanding 0.720s 50.402us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.760s 26.201us 1 1 100.00
pwrmgr_csr_rw 0.850s 19.457us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 54.546us 1 1 100.00
pwrmgr_same_csr_outstanding 0.720s 50.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.800s 11.062us 0 1 0.00
pwrmgr_sec_cm 0.760s 25.874us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.760s 25.874us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.760s 25.874us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.800s 11.062us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.290s 843.207us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.730s 67.932us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.870s 52.610us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.590s 41.207us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.760s 25.874us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.760s 25.874us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.760s 25.874us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.670s 63.570us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.620s 127.039us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.710s 55.442us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.850s 19.457us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.850s 19.457us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 1.040s 799.442us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 2.610s 800.043us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_tl_intg_err 67568120799910667270341797787708879021098171473421402598456428353753968808349 85
UVM_INFO @ 11061930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 104898149267754507026923330100806695956009544034127472472894656798240160216466 83
UVM_INFO @ 25873706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---