Simulation Results: rom_ctrl/32kb

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.36 %
  • code
  • 99.01 %
  • assert
  • 96.66 %
  • func
  • 96.42 %
  • line
  • 99.59 %
  • branch
  • 98.54 %
  • cond
  • 97.03 %
  • toggle
  • 99.87 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.070s 141.635us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.940s 231.243us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.900s 600.927us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.330s 213.496us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.210s 170.105us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.540s 136.233us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.900s 600.927us 1 1 100.00
rom_ctrl_csr_aliasing 4.210s 170.105us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.100s 474.821us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.130s 169.656us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.400s 227.706us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 11.020s 494.428us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 8.070s 315.148us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.700s 123.915us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.580s 169.550us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.580s 169.550us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.940s 231.243us 1 1 100.00
rom_ctrl_csr_rw 3.900s 600.927us 1 1 100.00
rom_ctrl_csr_aliasing 4.210s 170.105us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.900s 312.007us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.940s 231.243us 1 1 100.00
rom_ctrl_csr_rw 3.900s 600.927us 1 1 100.00
rom_ctrl_csr_aliasing 4.210s 170.105us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.900s 312.007us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.700s 3093.091us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.730s 2101.309us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 101.110s 1203.069us 1 1 100.00
rom_ctrl_tl_intg_err 22.800s 987.697us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 101.110s 1203.069us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 101.110s 1203.069us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.700s 3093.091us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.700s 3093.091us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.700s 3093.091us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.700s 3093.091us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.700s 3093.091us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 101.110s 1203.069us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 101.110s 1203.069us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.070s 141.635us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.070s 141.635us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.070s 141.635us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 22.800s 987.697us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.700s 3093.091us 1 1 100.00
rom_ctrl_kmac_err_chk 8.070s 315.148us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.700s 3093.091us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.700s 3093.091us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 52.700s 3093.091us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.730s 2101.309us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 101.110s 1203.069us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 173.330s 8942.331us 1 1 100.00