Simulation Results: rom_ctrl/64kb

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.53 %
  • code
  • 97.80 %
  • assert
  • 96.80 %
  • func
  • 94.99 %
  • line
  • 99.46 %
  • branch
  • 98.91 %
  • cond
  • 98.07 %
  • toggle
  • 99.24 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.770s 224.544us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.730s 428.773us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.720s 1276.822us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.260s 727.547us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.130s 207.711us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.760s 1599.371us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.720s 1276.822us 1 1 100.00
rom_ctrl_csr_aliasing 6.130s 207.711us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.850s 292.924us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.720s 360.232us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.720s 1077.738us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 16.790s 2154.592us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.830s 1424.481us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.120s 1063.921us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.130s 1216.351us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.130s 1216.351us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.730s 428.773us 1 1 100.00
rom_ctrl_csr_rw 6.720s 1276.822us 1 1 100.00
rom_ctrl_csr_aliasing 6.130s 207.711us 1 1 100.00
rom_ctrl_same_csr_outstanding 10.290s 307.116us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.730s 428.773us 1 1 100.00
rom_ctrl_csr_rw 6.720s 1276.822us 1 1 100.00
rom_ctrl_csr_aliasing 6.130s 207.711us 1 1 100.00
rom_ctrl_same_csr_outstanding 10.290s 307.116us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 136.600s 3443.604us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.160s 6353.783us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 228.430s 2503.310us 1 1 100.00
rom_ctrl_tl_intg_err 98.600s 432.962us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 228.430s 2503.310us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 228.430s 2503.310us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 136.600s 3443.604us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 136.600s 3443.604us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 136.600s 3443.604us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 136.600s 3443.604us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 136.600s 3443.604us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 228.430s 2503.310us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 228.430s 2503.310us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.770s 224.544us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.770s 224.544us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.770s 224.544us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 98.600s 432.962us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 136.600s 3443.604us 1 1 100.00
rom_ctrl_kmac_err_chk 12.830s 1424.481us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 136.600s 3443.604us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 136.600s 3443.604us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 136.600s 3443.604us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.160s 6353.783us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 228.430s 2503.310us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 23.250s 3453.437us 1 1 100.00