Simulation Results: rstmgr

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.29 %
  • code
  • 99.26 %
  • assert
  • 97.86 %
  • func
  • 97.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.54 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.270s 198.913us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.200s 125.827us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.000s 94.441us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.310s 1542.662us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.900s 209.748us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.150s 188.735us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.000s 94.441us 1 1 100.00
rstmgr_csr_aliasing 1.900s 209.748us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.990s 228.112us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.350s 136.776us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.070s 203.032us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.340s 2150.765us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.340s 2150.765us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.340s 2150.765us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.340s 2150.765us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 12.650s 4058.561us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.850s 86.329us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.660s 289.958us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.660s 289.958us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.200s 125.827us 1 1 100.00
rstmgr_csr_rw 1.000s 94.441us 1 1 100.00
rstmgr_csr_aliasing 1.900s 209.748us 1 1 100.00
rstmgr_same_csr_outstanding 1.420s 168.859us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.200s 125.827us 1 1 100.00
rstmgr_csr_rw 1.000s 94.441us 1 1 100.00
rstmgr_csr_aliasing 1.900s 209.748us 1 1 100.00
rstmgr_same_csr_outstanding 1.420s 168.859us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 10.960s 9168.820us 1 1 100.00
rstmgr_tl_intg_err 2.740s 829.415us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 10.960s 9168.820us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 10.960s 9168.820us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.740s 829.415us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.290s 143.246us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.110s 1276.994us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.180s 300.783us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 10.960s 9168.820us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.000s 94.441us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.000s 94.441us 1 1 100.00