Simulation Results: rstmgr_cnsty_chk

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Validation stages
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rstmgr_cnsty_chk_test 2.390s 11070.256us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *))
rstmgr_cnsty_chk_test 16393228443328306255936211058812998546972561815803679512365379111877915768313 175
UVM_INFO @ 2024696195 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 2044856195 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 2065016195 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 2085176195 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16
Job cancelled because all of its dependencies failed or were killed.
rstmgr_cnsty_chk None None
Job cancelled because one of its dependencies failed or was killed.
rstmgr_cnsty_chk None None