Simulation Results: rv_timer

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.23 %
  • code
  • 99.33 %
  • assert
  • 96.82 %
  • func
  • 83.53 %
  • line
  • 99.64 %
  • branch
  • 100.00 %
  • cond
  • 98.46 %
  • toggle
  • 99.22 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.880s 335.066us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.620s 30.301us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.540s 13.838us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.470s 288.483us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.920s 97.616us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.730s 16.841us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.540s 13.838us 1 1 100.00
rv_timer_csr_aliasing 0.920s 97.616us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.260s 2208.678us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.210s 1649.754us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 240.210s 203017.216us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 240.210s 203017.216us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.470s 961.946us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.610s 29.312us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.590s 15.477us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 0.860s 83.326us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 0.860s 83.326us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.620s 30.301us 1 1 100.00
rv_timer_csr_rw 0.540s 13.838us 1 1 100.00
rv_timer_csr_aliasing 0.920s 97.616us 1 1 100.00
rv_timer_same_csr_outstanding 0.680s 251.333us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.620s 30.301us 1 1 100.00
rv_timer_csr_rw 0.540s 13.838us 1 1 100.00
rv_timer_csr_aliasing 0.920s 97.616us 1 1 100.00
rv_timer_same_csr_outstanding 0.680s 251.333us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.840s 167.784us 1 1 100.00
rv_timer_tl_intg_err 0.810s 57.038us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.810s 57.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.640s 18.082us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.710s 90.138us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 4.740s 947.992us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 87833993631259368354325272738155471003512608355892497083437067037886962746436 75
UVM_INFO @ 90138163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 62826365637849105272140744086400675283602138633170982593923501791190919448704 75
UVM_INFO @ 2208678118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done)
rv_timer_stress_all_with_rand_reset 11828055574078175299904536126532746115186229001469211037387591227540345444974 140
UVM_INFO @ 947991854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---