Simulation Results: spi_device/1r1w

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.46 %
  • code
  • 93.19 %
  • assert
  • 94.64 %
  • func
  • 62.55 %
  • line
  • 99.02 %
  • branch
  • 98.20 %
  • cond
  • 95.83 %
  • toggle
  • 83.54 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 202.860s 36896.311us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.080s 121.392us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.080s 33.295us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 27.440s 9987.161us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 14.570s 1202.268us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.730s 128.126us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.080s 33.295us 1 1 100.00
spi_device_csr_aliasing 14.570s 1202.268us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.780s 33.267us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.420s 60.626us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.890s 13.782us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.770s 1.655us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.890s 4.383us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.890s 11.294us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.890s 11.294us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.840s 862.630us 1 1 100.00
spi_device_tpm_sts_read 0.840s 76.242us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 20.940s 2944.083us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 10.430s 2515.064us 1 1 100.00
spi_device_flash_all 20.670s 7488.604us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.650s 4485.351us 1 1 100.00
spi_device_flash_all 20.670s 7488.604us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.650s 4485.351us 1 1 100.00
spi_device_flash_all 20.670s 7488.604us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 20.670s 7488.604us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 11.130s 15691.861us 1 1 100.00
spi_device_flash_all 20.670s 7488.604us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 11.130s 15691.861us 1 1 100.00
spi_device_flash_all 20.670s 7488.604us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 11.130s 15691.861us 1 1 100.00
spi_device_flash_all 20.670s 7488.604us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 11.130s 15691.861us 1 1 100.00
spi_device_flash_all 20.670s 7488.604us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 11.130s 15691.861us 1 1 100.00
spi_device_flash_all 20.670s 7488.604us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 7.270s 32198.293us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 33.090s 18712.491us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 33.090s 18712.491us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 33.090s 18712.491us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 5.140s 327.554us 1 1 100.00
spi_device_read_buffer_direct 2.740s 245.825us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 33.090s 18712.491us 1 1 100.00
spi_device_flash_all 20.670s 7488.604us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 20.670s 7488.604us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 20.670s 7488.604us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 5.230s 1997.474us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 5.230s 1997.474us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 202.860s 36896.311us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 7.710s 1096.747us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 0.910s 74.797us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.760s 12.778us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.920s 14.446us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.620s 118.570us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.620s 118.570us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.080s 121.392us 1 1 100.00
spi_device_csr_rw 1.080s 33.295us 1 1 100.00
spi_device_csr_aliasing 14.570s 1202.268us 1 1 100.00
spi_device_same_csr_outstanding 2.310s 587.896us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.080s 121.392us 1 1 100.00
spi_device_csr_rw 1.080s 33.295us 1 1 100.00
spi_device_csr_aliasing 14.570s 1202.268us 1 1 100.00
spi_device_same_csr_outstanding 2.310s 587.896us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.880s 69.344us 1 1 100.00
spi_device_tl_intg_err 13.270s 623.884us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 13.270s 623.884us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 100.470s 44531.600us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 14569768745915200945044448845313536593209554592000387998779414987955316999953 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 863531 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 863531 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[986])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 68626125435523222418905388645582919381149198138710751194075439110212371907475 76
UVM_ERROR @ 1711176 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x93a1c2 [100100111010000111000010] vs 0x0 [0])
UVM_ERROR @ 1751176 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7cc12e [11111001100000100101110] vs 0x0 [0])
UVM_ERROR @ 1805176 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5893ca [10110001001001111001010] vs 0x0 [0])
UVM_ERROR @ 1859176 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1385f [10011100001011111] vs 0x0 [0])