Simulation Results: spi_device/2p

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.47 %
  • code
  • 94.19 %
  • assert
  • 94.62 %
  • func
  • 79.61 %
  • line
  • 99.16 %
  • branch
  • 98.46 %
  • cond
  • 96.22 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 292.460s 89380.771us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.020s 25.961us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.300s 45.828us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 24.000s 549.102us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 18.510s 2246.258us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.260s 195.431us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.300s 45.828us 1 1 100.00
spi_device_csr_aliasing 18.510s 2246.258us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.960s 36.405us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.340s 192.053us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.820s 35.789us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.130s 26.364us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.750s 23.371us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.730s 12.959us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.730s 12.959us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 8.720s 4613.168us 1 1 100.00
spi_device_tpm_sts_read 0.820s 544.875us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 26.350s 47953.060us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 7.020s 5853.600us 1 1 100.00
spi_device_flash_all 22.550s 5488.877us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.240s 1240.090us 1 1 100.00
spi_device_flash_all 22.550s 5488.877us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.240s 1240.090us 1 1 100.00
spi_device_flash_all 22.550s 5488.877us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 22.550s 5488.877us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 8.070s 1126.883us 1 1 100.00
spi_device_flash_all 22.550s 5488.877us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 8.070s 1126.883us 1 1 100.00
spi_device_flash_all 22.550s 5488.877us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 8.070s 1126.883us 1 1 100.00
spi_device_flash_all 22.550s 5488.877us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 8.070s 1126.883us 1 1 100.00
spi_device_flash_all 22.550s 5488.877us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 8.070s 1126.883us 1 1 100.00
spi_device_flash_all 22.550s 5488.877us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 1.870s 395.442us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 3.710s 186.592us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 3.710s 186.592us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 3.710s 186.592us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 7.640s 667.690us 1 1 100.00
spi_device_read_buffer_direct 3.340s 2655.235us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 3.710s 186.592us 1 1 100.00
spi_device_flash_all 22.550s 5488.877us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 22.550s 5488.877us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 22.550s 5488.877us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 5.320s 488.751us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 5.320s 488.751us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 292.460s 89380.771us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 88.650s 18113.253us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 369.050s 348060.894us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.830s 16.358us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.720s 31.617us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.730s 2071.308us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.730s 2071.308us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.020s 25.961us 1 1 100.00
spi_device_csr_rw 1.300s 45.828us 1 1 100.00
spi_device_csr_aliasing 18.510s 2246.258us 1 1 100.00
spi_device_same_csr_outstanding 3.070s 291.249us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.020s 25.961us 1 1 100.00
spi_device_csr_rw 1.300s 45.828us 1 1 100.00
spi_device_csr_aliasing 18.510s 2246.258us 1 1 100.00
spi_device_same_csr_outstanding 3.070s 291.249us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.640s 320.454us 1 1 100.00
spi_device_tl_intg_err 12.360s 562.342us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 12.360s 562.342us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 69.490s 144468.059us 1 1 100.00