Simulation Results: sram_ctrl/main

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.35 %
  • code
  • 96.78 %
  • assert
  • 96.46 %
  • func
  • 92.80 %
  • block
  • 96.08 %
  • line
  • 96.88 %
  • branch
  • 94.17 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 375.913us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 24.070us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 61.677us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 28.644us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 27.165us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 743.529us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 61.677us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 27.165us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 81.000s 4201.735us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 54.000s 3011.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 25.000s 62266.417us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 166.000s 32337.560us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 120.000s 11375.709us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 26.000s 19913.540us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 48.000s 51453.146us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 19.000s 3530.292us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 704.702us 1 1 100.00
sram_ctrl_partial_access_b2b 196.000s 14514.278us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 6.000s 676.650us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 3166.725us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 4789.268us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 6.000s 395.853us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 962.050us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 140.000s 55745.105us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 43.558us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 26.951us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 26.951us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 24.070us 1 1 100.00
sram_ctrl_csr_rw 2.000s 61.677us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 27.165us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 38.882us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 24.070us 1 1 100.00
sram_ctrl_csr_rw 2.000s 61.677us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 27.165us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 38.882us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 8098.378us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 378.542us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 531.473us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 378.542us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 531.473us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 395.853us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 6.000s 395.853us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 61.677us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 19.000s 3530.292us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 19.000s 3530.292us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 19.000s 3530.292us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 48.000s 51453.146us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 698.041us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 8098.378us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 679.920us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 375.913us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 375.913us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 19.000s 3530.292us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 378.542us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 48.000s 51453.146us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 378.542us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 378.542us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 375.913us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 378.542us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 12.000s 6349.751us 1 1 100.00