Simulation Results: sysrst_ctrl

 
27/04/2026 15:30:28 DVSim: v1.32.0 sha: ef57538 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.66 %
  • code
  • 89.27 %
  • assert
  • 88.03 %
  • func
  • 67.68 %
  • line
  • 95.29 %
  • branch
  • 96.07 %
  • cond
  • 92.83 %
  • toggle
  • 100.00 %
  • FSM
  • 62.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.910s 2113.519us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.980s 2482.296us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.600s 2444.129us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.430s 2333.527us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.860s 6082.859us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 5.100s 2060.283us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 67.580s 76157.208us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.000s 3116.265us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.670s 2084.953us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 5.100s 2060.283us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.000s 3116.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 135.700s 68708.268us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 138.770s 80064.201us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 4.560s 4003.758us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 2.210s 3124.892us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 6.340s 2511.378us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.570s 2144.456us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.450s 2950.831us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.840s 2616.807us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 6.130s 5636.352us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 15.370s 32508.044us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 14.460s 8828.647us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 4.690s 2012.012us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 5.050s 2011.668us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.480s 2028.726us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.480s 2028.726us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.860s 6082.859us 1 1 100.00
sysrst_ctrl_csr_rw 5.100s 2060.283us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.000s 3116.265us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.250s 6959.845us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.860s 6082.859us 1 1 100.00
sysrst_ctrl_csr_rw 5.100s 2060.283us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.000s 3116.265us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.250s 6959.845us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 78.000s 42013.050us 1 1 100.00
sysrst_ctrl_tl_intg_err 47.460s 22228.491us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 47.460s 22228.491us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 7.680s 3827.780us 1 1 100.00