Simulation Results: adc_ctrl

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 64.92 %
  • code
  • 91.58 %
  • assert
  • 90.44 %
  • func
  • 12.74 %
  • line
  • 97.97 %
  • branch
  • 96.23 %
  • cond
  • 86.02 %
  • toggle
  • 99.29 %
  • FSM
  • 78.38 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 10.960s 5867.670us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.160s 974.114us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.050s 487.762us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 13.920s 26351.213us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.310s 1300.883us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.070s 526.915us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.050s 487.762us 1 1 100.00
adc_ctrl_csr_aliasing 2.310s 1300.883us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.260s 386.920us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.270s 474.192us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.700s 509.583us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.870s 498.394us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.950s 346.707us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.900s 379.417us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.920s 379.291us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.840s 383.183us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 6.630s 4012.369us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 17.020s 36541.062us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 28.700s 69779.348us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 1.810s 739.770us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.970s 373.886us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.170s 530.867us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.820s 568.188us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.820s 568.188us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.160s 974.114us 1 1 100.00
adc_ctrl_csr_rw 1.050s 487.762us 1 1 100.00
adc_ctrl_csr_aliasing 2.310s 1300.883us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.670s 2363.263us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.160s 974.114us 1 1 100.00
adc_ctrl_csr_rw 1.050s 487.762us 1 1 100.00
adc_ctrl_csr_aliasing 2.310s 1300.883us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.670s 2363.263us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 2.610s 4349.854us 1 1 100.00
adc_ctrl_tl_intg_err 9.250s 4434.074us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 9.250s 4434.074us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 0.920s 924.566us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *]
adc_ctrl_filters_polled 61105054722792154023456480597924451386573617697261182069440269985889040932696 389
UVM_INFO @ 386919947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 93417305511470912706907175020820103229151574612638015982672211861003961990057 389
UVM_INFO @ 474192209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 91121258816453671818233998024328986580502543155665364170269429656267521511229 389
UVM_INFO @ 509582558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 59476392254004681913043170400177389406334101768299667327696502800363730003202 389
UVM_INFO @ 498393699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 14677367281204982695339443300456097170182711304617555326561432952659182024506 389
UVM_INFO @ 346706932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 114037539537170294377531640996617475543374113798522590520699473326235574256684 389
UVM_INFO @ 379417488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 5291121346761308975242395674773085858733624470684155593022351550398747604105 389
UVM_INFO @ 383182515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 107225449521391243756109898859378440818520587745978536602935918540628983566092 389
UVM_INFO @ 379290651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 7513739482005998998350126623420374842514992947884190999832972638374543234029 395
UVM_INFO @ 924565504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 33862073347216645172079867141732790063742129217288130633203040918041096567673 390
UVM_INFO @ 739770188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---