Simulation Results: aes/masked

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.39 %
  • code
  • 95.62 %
  • assert
  • 98.43 %
  • func
  • 65.12 %
  • block
  • 95.77 %
  • line
  • 97.44 %
  • branch
  • 89.56 %
  • toggle
  • 98.05 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
89.47%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 100.698us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 90.668us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 52.469us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 80.722us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 190.851us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 230.994us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 70.903us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 80.722us 1 1 100.00
aes_csr_aliasing 3.000s 230.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 90.668us 1 1 100.00
aes_config_error 3.000s 255.862us 1 1 100.00
aes_stress 3.000s 111.420us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 90.668us 1 1 100.00
aes_config_error 3.000s 255.862us 1 1 100.00
aes_stress 3.000s 111.420us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 111.420us 1 1 100.00
aes_b2b 17.000s 586.416us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 111.420us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 90.668us 1 1 100.00
aes_config_error 3.000s 255.862us 1 1 100.00
aes_stress 3.000s 111.420us 1 1 100.00
aes_alert_reset 27.000s 10060.926us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 66.781us 1 1 100.00
aes_config_error 3.000s 255.862us 1 1 100.00
aes_alert_reset 27.000s 10060.926us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 114.598us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 645.405us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 7.000s 555.099us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 27.000s 10060.926us 0 1 0.00
stress 1 1 100.00
aes_stress 3.000s 111.420us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 111.420us 1 1 100.00
aes_sideload 3.000s 78.853us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 179.933us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 21.000s 10099.021us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 79.933us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 68.692us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 93.001us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 93.001us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 52.469us 1 1 100.00
aes_csr_rw 2.000s 80.722us 1 1 100.00
aes_csr_aliasing 3.000s 230.994us 1 1 100.00
aes_same_csr_outstanding 2.000s 115.305us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 52.469us 1 1 100.00
aes_csr_rw 2.000s 80.722us 1 1 100.00
aes_csr_aliasing 3.000s 230.994us 1 1 100.00
aes_same_csr_outstanding 2.000s 115.305us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 131.074us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 32.000s 10011.077us 0 1 0.00
aes_control_fi 2.000s 62.970us 1 1 100.00
aes_cipher_fi 3.000s 74.606us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 96.220us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 96.220us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 96.220us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 96.220us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 538.845us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 7.000s 5446.874us 1 1 100.00
aes_tl_intg_err 3.000s 633.702us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 633.702us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 27.000s 10060.926us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 96.220us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 96.220us 1 1 100.00
sec_cm_main_config_sparse 2 4 50.00
aes_smoke 2.000s 90.668us 1 1 100.00
aes_stress 3.000s 111.420us 1 1 100.00
aes_alert_reset 27.000s 10060.926us 0 1 0.00
aes_core_fi 26.000s 10048.779us 0 1 0.00
sec_cm_gcm_config_sparse 3 4 75.00
aes_gcm_save_restore 2.000s 79.933us 1 1 100.00
aes_config_error 3.000s 255.862us 1 1 100.00
aes_stress 3.000s 111.420us 1 1 100.00
aes_core_fi 26.000s 10048.779us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 96.220us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 75.552us 1 1 100.00
aes_stress 3.000s 111.420us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 111.420us 1 1 100.00
aes_sideload 3.000s 78.853us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 75.552us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 75.552us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 75.552us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 75.552us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 75.552us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 111.420us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 111.420us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 32.000s 10011.077us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 32.000s 10011.077us 0 1 0.00
aes_control_fi 2.000s 62.970us 1 1 100.00
aes_cipher_fi 3.000s 74.606us 1 1 100.00
aes_ctr_fi 2.000s 50.605us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 32.000s 10011.077us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 32.000s 10011.077us 0 1 0.00
aes_control_fi 2.000s 62.970us 1 1 100.00
aes_cipher_fi 3.000s 74.606us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 74.606us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 32.000s 10011.077us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 32.000s 10011.077us 0 1 0.00
aes_control_fi 2.000s 62.970us 1 1 100.00
aes_ctr_fi 2.000s 50.605us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 32.000s 10011.077us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 32.000s 10011.077us 0 1 0.00
aes_control_fi 2.000s 62.970us 1 1 100.00
aes_cipher_fi 3.000s 74.606us 1 1 100.00
aes_ctr_fi 2.000s 50.605us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 27.000s 10060.926us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 32.000s 10011.077us 0 1 0.00
aes_control_fi 2.000s 62.970us 1 1 100.00
aes_cipher_fi 3.000s 74.606us 1 1 100.00
aes_ctr_fi 2.000s 50.605us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 32.000s 10011.077us 0 1 0.00
aes_control_fi 2.000s 62.970us 1 1 100.00
aes_cipher_fi 3.000s 74.606us 1 1 100.00
aes_ctr_fi 2.000s 50.605us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 32.000s 10011.077us 0 1 0.00
aes_control_fi 2.000s 62.970us 1 1 100.00
aes_ctr_fi 2.000s 50.605us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 32.000s 10011.077us 0 1 0.00
aes_ghash_fi 2.000s 63.203us 1 1 100.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 32.000s 10011.077us 0 1 0.00
aes_control_fi 2.000s 62.970us 1 1 100.00
aes_cipher_fi 3.000s 74.606us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 27.000s 1318.080us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 74481419362563696072255620926337347475080571229920507347033264908254350888424 2174
UVM_INFO @ 10060926285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 43436081901356353165941292923972721591608998276976725842874779909484258373137 1877
UVM_INFO @ 10099021365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 73770074562571897253037953511963972121006485246057824366358953443504595151320 1320
UVM_INFO @ 10011076724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_core_fi_vseq] wait timeout occurred!
aes_core_fi 16513689723750976609732750426675914634349643749382478272300240116067803565329 139
UVM_INFO @ 10048779135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 47813337468811557456392624957134648423005379274227708905917696828459010848423 905
UVM_INFO @ 1318079528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---