Simulation Results: aes/unmasked

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.19 %
  • code
  • 91.26 %
  • assert
  • 97.94 %
  • func
  • 66.36 %
  • block
  • 90.77 %
  • line
  • 93.00 %
  • branch
  • 83.27 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
89.47%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 80.642us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 86.269us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 65.342us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 66.447us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 343.866us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 264.194us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 131.346us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 66.447us 1 1 100.00
aes_csr_aliasing 3.000s 264.194us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 86.269us 1 1 100.00
aes_config_error 3.000s 401.973us 1 1 100.00
aes_stress 2.000s 118.076us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 86.269us 1 1 100.00
aes_config_error 3.000s 401.973us 1 1 100.00
aes_stress 2.000s 118.076us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 118.076us 1 1 100.00
aes_b2b 2.000s 71.079us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 118.076us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 86.269us 1 1 100.00
aes_config_error 3.000s 401.973us 1 1 100.00
aes_stress 2.000s 118.076us 1 1 100.00
aes_alert_reset 30.000s 10012.972us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 96.567us 1 1 100.00
aes_config_error 3.000s 401.973us 1 1 100.00
aes_alert_reset 30.000s 10012.972us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 221.695us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 360.073us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 4.000s 416.621us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 30.000s 10012.972us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 118.076us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 118.076us 1 1 100.00
aes_sideload 2.000s 130.282us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 417.475us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 19.000s 10712.434us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 2.000s 169.255us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 112.723us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 85.738us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 85.738us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 65.342us 1 1 100.00
aes_csr_rw 1.000s 66.447us 1 1 100.00
aes_csr_aliasing 3.000s 264.194us 1 1 100.00
aes_same_csr_outstanding 2.000s 113.938us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 65.342us 1 1 100.00
aes_csr_rw 1.000s 66.447us 1 1 100.00
aes_csr_aliasing 3.000s 264.194us 1 1 100.00
aes_same_csr_outstanding 2.000s 113.938us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 69.400us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 8.000s 10030.073us 0 1 0.00
aes_control_fi 2.000s 64.878us 1 1 100.00
aes_cipher_fi 17.000s 10004.633us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 536.976us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 536.976us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 536.976us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 536.976us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 197.786us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1192.050us 1 1 100.00
aes_tl_intg_err 3.000s 187.099us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 187.099us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 30.000s 10012.972us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 536.976us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 536.976us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 86.269us 1 1 100.00
aes_stress 2.000s 118.076us 1 1 100.00
aes_alert_reset 30.000s 10012.972us 0 1 0.00
aes_core_fi 3.000s 99.201us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 2.000s 169.255us 1 1 100.00
aes_config_error 3.000s 401.973us 1 1 100.00
aes_stress 2.000s 118.076us 1 1 100.00
aes_core_fi 3.000s 99.201us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 536.976us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 102.214us 1 1 100.00
aes_stress 2.000s 118.076us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 118.076us 1 1 100.00
aes_sideload 2.000s 130.282us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 102.214us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 102.214us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 102.214us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 102.214us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 102.214us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 118.076us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 118.076us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 8.000s 10030.073us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 8.000s 10030.073us 0 1 0.00
aes_control_fi 2.000s 64.878us 1 1 100.00
aes_cipher_fi 17.000s 10004.633us 0 1 0.00
aes_ctr_fi 2.000s 90.609us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 8.000s 10030.073us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 8.000s 10030.073us 0 1 0.00
aes_control_fi 2.000s 64.878us 1 1 100.00
aes_cipher_fi 17.000s 10004.633us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 17.000s 10004.633us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 8.000s 10030.073us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 8.000s 10030.073us 0 1 0.00
aes_control_fi 2.000s 64.878us 1 1 100.00
aes_ctr_fi 2.000s 90.609us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 8.000s 10030.073us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 8.000s 10030.073us 0 1 0.00
aes_control_fi 2.000s 64.878us 1 1 100.00
aes_cipher_fi 17.000s 10004.633us 0 1 0.00
aes_ctr_fi 2.000s 90.609us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 30.000s 10012.972us 0 1 0.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 8.000s 10030.073us 0 1 0.00
aes_control_fi 2.000s 64.878us 1 1 100.00
aes_cipher_fi 17.000s 10004.633us 0 1 0.00
aes_ctr_fi 2.000s 90.609us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 8.000s 10030.073us 0 1 0.00
aes_control_fi 2.000s 64.878us 1 1 100.00
aes_cipher_fi 17.000s 10004.633us 0 1 0.00
aes_ctr_fi 2.000s 90.609us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 8.000s 10030.073us 0 1 0.00
aes_control_fi 2.000s 64.878us 1 1 100.00
aes_ctr_fi 2.000s 90.609us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_fi 8.000s 10030.073us 0 1 0.00
aes_ghash_fi 1.000s 52.109us 1 1 100.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 8.000s 10030.073us 0 1 0.00
aes_control_fi 2.000s 64.878us 1 1 100.00
aes_cipher_fi 17.000s 10004.633us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 42.000s 1137.522us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [aes_alert_reset_vseq] wait timeout occurred!
aes_alert_reset 25979509520187485428540789881837858389010928728100937244670516933757002481086 943
UVM_INFO @ 10012971706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 115376400314770930190860590400312010866107136600900247266586383554876862344986 26725
UVM_INFO @ 10712434092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [aes_fi_vseq] wait timeout occurred!
aes_fi 44864692201662358848647972477021828224426318573923444453650473918627857473966 1335
UVM_INFO @ 10030072748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
aes_cipher_fi 80307126304551356309687704197295003823391130339277048621664358602299497579240 150
UVM_INFO @ 10004632595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
aes_stress_all_with_rand_reset 89357896217257253265412489277484845378791043306543613957968079178012249137361 1127
UVM_INFO @ 1137521533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---