Simulation Results: alert_handler

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.70 %
  • code
  • 90.82 %
  • assert
  • 98.33 %
  • func
  • 76.95 %
  • line
  • 99.65 %
  • branch
  • 98.10 %
  • cond
  • 90.95 %
  • toggle
  • 91.23 %
  • FSM
  • 74.19 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 20.210s 522.468us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.370s 61.976us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 2.590s 67.775us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 231.990s 22793.901us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 44.550s 1119.799us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.080s 197.447us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 2.590s 67.775us 1 1 100.00
alert_handler_csr_aliasing 44.550s 1119.799us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 79.590s 11761.910us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 13.100s 335.867us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 708.640s 13654.976us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 19.390s 913.957us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 20.210s 522.468us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 21.410s 372.093us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 24.380s 1197.989us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 247.570s 86178.746us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 708.030s 12992.171us 1 1 100.00
alert_handler_lpg_stub_clk 1938.890s 71575.265us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 28.800s 2867.132us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 8.680s 402.799us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.320s 33.345us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.630s 7.805us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 7.340s 130.651us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 7.340s 130.651us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.370s 61.976us 1 1 100.00
alert_handler_csr_rw 2.590s 67.775us 1 1 100.00
alert_handler_csr_aliasing 44.550s 1119.799us 1 1 100.00
alert_handler_same_csr_outstanding 16.530s 1401.714us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.370s 61.976us 1 1 100.00
alert_handler_csr_rw 2.590s 67.775us 1 1 100.00
alert_handler_csr_aliasing 44.550s 1119.799us 1 1 100.00
alert_handler_same_csr_outstanding 16.530s 1401.714us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 109.090s 2595.641us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 109.090s 2595.641us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 109.090s 2595.641us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 109.090s 2595.641us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 417.830s 18582.175us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 9.120s 880.522us 1 1 100.00
alert_handler_tl_intg_err 26.550s 638.293us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 26.550s 638.293us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 109.090s 2595.641us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 20.210s 522.468us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 20.210s 522.468us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 20.210s 522.468us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 20.210s 522.468us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 19.390s 913.957us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 708.030s 12992.171us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 19.390s 913.957us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 708.640s 13654.976us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 708.640s 13654.976us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.120s 880.522us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 9.120s 880.522us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.120s 880.522us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 9.120s 880.522us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 9.120s 880.522us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.120s 880.522us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.120s 880.522us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 9.120s 880.522us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 9.120s 880.522us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 11.160s 270.773us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 53112844754323648175131879458203377865928352092020019966969936614703768347144 139
UVM_INFO @ 86178745668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 22772513083560876324994907700583298773893312561907070944549522339450762348757 94
UVM_INFO @ 270773268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---