Simulation Results: chip

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.69 %
  • code
  • 85.08 %
  • assert
  • 97.37 %
  • func
  • 29.61 %
  • line
  • 94.23 %
  • branch
  • 93.77 %
  • cond
  • 88.90 %
  • toggle
  • 91.38 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
77.70%
V2S
100.00%
V3
65.38%
unmapped
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 194.810s 3547.877us 1 1 100.00
chip_sw_example_rom 87.580s 2771.052us 1 1 100.00
chip_sw_example_manufacturer 129.040s 3049.494us 1 1 100.00
chip_sw_example_concurrency 179.360s 3357.175us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 301.590s 7509.482us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 414.600s 6015.909us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 756.640s 9044.792us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3653.070s 29269.437us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 52.330s 2218.123us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3653.070s 29269.437us 1 1 100.00
chip_csr_rw 414.600s 6015.909us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.330s 206.295us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 286.170s 4924.450us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 286.170s 4924.450us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 286.170s 4924.450us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 366.380s 4290.251us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 366.380s 4290.251us 1 1 100.00
chip_sw_uart_tx_rx_idx1 421.830s 4482.384us 1 1 100.00
chip_sw_uart_tx_rx_idx2 391.030s 4622.453us 1 1 100.00
chip_sw_uart_tx_rx_idx3 387.990s 4364.629us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 339.600s 4107.004us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1835.460s 12851.614us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 682.270s 9123.747us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 156.360s 4810.047us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 156.360s 4810.047us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 187.020s 2702.083us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 153.820s 2970.360us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 226.410s 4557.748us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 278.330s 5239.346us 1 1 100.00
chip_tap_straps_testunlock0 227.600s 5089.921us 1 1 100.00
chip_tap_straps_rma 98.920s 3278.478us 1 1 100.00
chip_tap_straps_prod 75.130s 2710.947us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 132.810s 2569.847us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 765.330s 8712.548us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 438.800s 5358.663us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 438.800s 5358.663us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 577.890s 8175.473us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1146.490s 10811.939us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 353.620s 4625.484us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 564.250s 5783.308us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3774.860s 20024.517us 1 1 100.00
chip_sw_aes_enc_jitter_en 170.470s 3157.823us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 776.550s 7090.533us 1 1 100.00
chip_sw_hmac_enc_jitter_en 152.690s 3324.973us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 868.590s 9075.770us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 183.200s 3062.179us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 363.070s 5156.245us 1 1 100.00
chip_sw_clkmgr_jitter 136.200s 2618.518us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 221.950s 3507.281us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 730.100s 10209.548us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 222.670s 5119.902us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 167.560s 3181.858us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 222.670s 5119.902us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 172.570s 3110.119us 1 1 100.00
chip_sw_aes_smoketest 207.760s 3843.130us 1 1 100.00
chip_sw_aon_timer_smoketest 174.700s 3306.913us 1 1 100.00
chip_sw_clkmgr_smoketest 176.900s 3352.649us 1 1 100.00
chip_sw_csrng_smoketest 140.510s 3023.660us 1 1 100.00
chip_sw_entropy_src_smoketest 981.130s 7963.926us 1 1 100.00
chip_sw_gpio_smoketest 189.180s 2743.945us 1 1 100.00
chip_sw_hmac_smoketest 236.590s 2927.354us 1 1 100.00
chip_sw_kmac_smoketest 200.420s 2965.541us 1 1 100.00
chip_sw_otbn_smoketest 813.550s 6937.097us 1 1 100.00
chip_sw_pwrmgr_smoketest 348.360s 5328.380us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 246.090s 5607.720us 1 1 100.00
chip_sw_rv_plic_smoketest 139.270s 2946.109us 1 1 100.00
chip_sw_rv_timer_smoketest 177.370s 2736.430us 1 1 100.00
chip_sw_rstmgr_smoketest 127.240s 2465.883us 1 1 100.00
chip_sw_sram_ctrl_smoketest 126.640s 2688.843us 1 1 100.00
chip_sw_uart_smoketest 155.510s 3148.015us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 134.240s 3007.279us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 287.570s 5429.749us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7943.020s 62420.533us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2960.030s 15183.456us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 117.311s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 213.480s 3350.440us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 182.070s 2785.410us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7105.190s 55668.717us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 8035.770s 58797.946us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 190.990s 4162.731us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 190.990s 4162.731us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3653.070s 29269.437us 1 1 100.00
chip_same_csr_outstanding 2562.520s 30096.540us 1 1 100.00
chip_csr_hw_reset 301.590s 7509.482us 1 1 100.00
chip_csr_rw 414.600s 6015.909us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3653.070s 29269.437us 1 1 100.00
chip_same_csr_outstanding 2562.520s 30096.540us 1 1 100.00
chip_csr_hw_reset 301.590s 7509.482us 1 1 100.00
chip_csr_rw 414.600s 6015.909us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 25.310s 397.975us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.540s 48.025us 1 1 100.00
xbar_smoke_large_delays 37.010s 5900.457us 1 1 100.00
xbar_smoke_slow_rsp 34.150s 3672.599us 1 1 100.00
xbar_random_zero_delays 5.970s 68.109us 1 1 100.00
xbar_random_large_delays 100.690s 17869.851us 1 1 100.00
xbar_random_slow_rsp 16.470s 1637.927us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 19.370s 218.826us 1 1 100.00
xbar_error_and_unmapped_addr 22.910s 840.491us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 27.370s 557.293us 1 1 100.00
xbar_error_and_unmapped_addr 22.910s 840.491us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 22.460s 842.781us 1 1 100.00
xbar_access_same_device_slow_rsp 27.880s 2777.124us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 41.670s 2301.788us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 29.860s 383.727us 1 1 100.00
xbar_stress_all_with_error 48.940s 973.034us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 15.470s 62.987us 1 1 100.00
xbar_stress_all_with_reset_error 155.860s 2190.687us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2960.030s 15183.456us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2464.440s 26358.041us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2930.020s 15539.875us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 123.815s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 9.726s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 10.558s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 9.686s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 7.712s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 128.750s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 53.738s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 56.268s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 36.216s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 23.678s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 67.784s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 71.604s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 74.822s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 85.176s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 178.035s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 19.980s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 17.790s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.950s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 17.440s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 16.780s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 17.200s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 19.080s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 18.220s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 17.480s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 20.730s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 17.110s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 17.580s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 17.730s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 17.380s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 16.930s 10.140us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 131.622s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 18.411s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 18.162s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 7.676s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 9.970s 0.000us 0 1 0.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 5919.370s 29942.736us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 3206.360s 17149.072us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5896.760s 28986.020us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3277.490s 15687.218us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2924.570s 34694.274us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2924.570s 34694.274us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 172.280s 3378.051us 1 1 100.00
chip_sw_aes_enc_jitter_en 170.470s 3157.823us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 138.580s 3263.075us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 206.450s 3179.953us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 921.830s 9121.852us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 195.130s 3544.892us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 384.730s 5524.779us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 426.810s 5438.307us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 587.900s 5868.730us 1 1 100.00
chip_plic_all_irqs_10 319.590s 3882.813us 1 1 100.00
chip_plic_all_irqs_20 308.690s 3806.264us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 176.240s 3443.597us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1144.320s 13794.484us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 279.780s 4774.435us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 142.420s 3345.915us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 607.530s 5425.975us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 909.730s 7536.572us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 891.590s 8499.002us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 7863.200s 256155.731us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 257.910s 4011.720us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 348.360s 5328.380us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 257.910s 4011.720us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 449.370s 7967.328us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 449.370s 7967.328us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 293.700s 6802.392us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 353.560s 5143.761us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 566.710s 5877.343us 1 1 100.00
chip_sw_aes_idle 206.450s 3179.953us 1 1 100.00
chip_sw_hmac_enc_idle 142.290s 2641.371us 1 1 100.00
chip_sw_kmac_idle 171.260s 2674.583us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 365.940s 4953.698us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 302.520s 5214.533us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 279.990s 3749.497us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 345.860s 5204.468us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 748.680s 9452.002us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 364.880s 4011.913us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 398.700s 5357.708us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 409.370s 4072.761us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 332.330s 4650.093us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 362.060s 4675.798us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 393.560s 5109.344us 1 1 100.00
chip_sw_ast_clk_outputs 577.890s 8175.473us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 632.510s 13201.116us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 409.370s 4072.761us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 332.330s 4650.093us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 353.620s 4625.484us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 564.250s 5783.308us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3774.860s 20024.517us 1 1 100.00
chip_sw_aes_enc_jitter_en 170.470s 3157.823us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 776.550s 7090.533us 1 1 100.00
chip_sw_hmac_enc_jitter_en 152.690s 3324.973us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 868.590s 9075.770us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 183.200s 3062.179us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 363.070s 5156.245us 1 1 100.00
chip_sw_clkmgr_jitter 136.200s 2618.518us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 131.240s 2790.373us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 390.720s 4877.945us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 633.260s 7214.058us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4034.410s 25262.721us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 166.730s 3287.709us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 184.570s 2987.180us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1026.290s 12084.690us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 193.410s 3323.784us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 420.270s 5655.595us 1 1 100.00
chip_sw_flash_init_reduced_freq 1295.220s 24668.782us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 3349.160s 25201.671us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 577.890s 8175.473us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 370.230s 4246.794us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 247.090s 3569.342us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 426.810s 5438.307us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 607.530s 5425.975us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2105.480s 24219.007us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 141.610s 2490.207us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 518.320s 7905.658us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 134.300s 2848.389us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 5416.070s 30810.171us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 200.440s 3238.036us 1 1 100.00
chip_sw_edn_entropy_reqs 613.100s 6440.003us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 200.440s 3238.036us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2105.480s 24219.007us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 155.500s 3049.750us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1205.770s 24422.918us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 563.390s 5169.068us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 564.250s 5783.308us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 327.790s 3682.545us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 353.620s 4625.484us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3682.240s 43484.097us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1205.770s 24422.918us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 232.900s 3674.335us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 801.210s 7584.073us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 166.960s 2826.892us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3682.240s 43484.097us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 166.960s 2826.892us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 166.960s 2826.892us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 166.960s 2826.892us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 166.960s 2826.892us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 426.810s 5438.307us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 166.280s 6011.261us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 498.680s 5254.963us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 496.560s 6337.352us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 496.560s 6337.352us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 200.250s 3261.595us 1 1 100.00
chip_sw_hmac_enc_jitter_en 152.690s 3324.973us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 142.290s 2641.371us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 876.730s 6638.173us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 750.170s 5497.797us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 445.770s 5177.458us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 487.160s 5380.961us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 384.350s 5055.197us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 237.480s 4324.041us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 801.210s 7584.073us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 868.590s 9075.770us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 941.850s 7766.645us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 921.830s 9121.852us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2466.290s 13598.914us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 189.860s 3269.060us 1 1 100.00
chip_sw_kmac_mode_kmac 209.030s 3288.311us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 183.200s 3062.179us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 801.210s 7584.073us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 331.950s 5728.898us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 159.110s 3217.266us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1376.570s 10186.489us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 171.260s 2674.583us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 384.730s 5524.779us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 278.330s 5239.346us 1 1 100.00
chip_tap_straps_rma 98.920s 3278.478us 1 1 100.00
chip_tap_straps_prod 75.130s 2710.947us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 201.710s 3603.674us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 331.950s 5728.898us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 331.950s 5728.898us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 331.950s 5728.898us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1701.330s 13644.520us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 166.960s 2826.892us 0 1 0.00
chip_sw_flash_rma_unlocked 3682.240s 43484.097us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 188.190s 3141.083us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 636.840s 5993.674us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 465.480s 5180.496us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 415.810s 6526.017us 0 1 0.00
chip_sw_lc_ctrl_transition 331.950s 5728.898us 1 1 100.00
chip_sw_keymgr_key_derivation 801.210s 7584.073us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 383.420s 8927.899us 1 1 100.00
chip_sw_sram_ctrl_execution_main 486.760s 9403.537us 1 1 100.00
chip_prim_tl_access 166.280s 6011.261us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 632.510s 13201.116us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 364.880s 4011.913us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 398.700s 5357.708us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 409.370s 4072.761us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 332.330s 4650.093us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 362.060s 4675.798us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 393.560s 5109.344us 1 1 100.00
chip_tap_straps_dev 278.330s 5239.346us 1 1 100.00
chip_tap_straps_rma 98.920s 3278.478us 1 1 100.00
chip_tap_straps_prod 75.130s 2710.947us 1 1 100.00
chip_rv_dm_lc_disabled 288.690s 10300.617us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 155.810s 3342.959us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 77.480s 3164.132us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 92.770s 3344.482us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 129.860s 2886.484us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1488.410s 24778.473us 1 1 100.00
chip_rv_dm_lc_disabled 288.690s 10300.617us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 542.930s 8196.787us 0 1 0.00
chip_sw_lc_walkthrough_prod 647.400s 9943.778us 0 1 0.00
chip_sw_lc_walkthrough_prodend 723.380s 8711.626us 1 1 100.00
chip_sw_lc_walkthrough_rma 356.200s 5695.216us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1488.410s 24778.473us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 61.000s 2037.943us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 55.900s 2338.409us 1 1 100.00
rom_volatile_raw_unlock 115.563s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3750.920s 17285.407us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3774.860s 20024.517us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 566.710s 5877.343us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 566.710s 5877.343us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 566.710s 5877.343us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 258.530s 3505.045us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 331.950s 5728.898us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1205.770s 24422.918us 1 1 100.00
chip_sw_otbn_mem_scramble 258.530s 3505.045us 1 1 100.00
chip_sw_keymgr_key_derivation 801.210s 7584.073us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 497.610s 5761.484us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 146.750s 3061.126us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1205.770s 24422.918us 1 1 100.00
chip_sw_otbn_mem_scramble 258.530s 3505.045us 1 1 100.00
chip_sw_keymgr_key_derivation 801.210s 7584.073us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 497.610s 5761.484us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 146.750s 3061.126us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 331.950s 5728.898us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 303.340s 5081.017us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 201.710s 3603.674us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 188.190s 3141.083us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 636.840s 5993.674us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 465.480s 5180.496us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 415.810s 6526.017us 0 1 0.00
chip_sw_lc_ctrl_transition 331.950s 5728.898us 1 1 100.00
chip_prim_tl_access 166.280s 6011.261us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 166.280s 6011.261us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 931.930s 7511.987us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 63.750s 3114.146us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1192.340s 26011.346us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 282.140s 8049.397us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 367.700s 7393.516us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 352.890s 7557.273us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1019.550s 22016.589us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 237.160s 6218.976us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 449.370s 7967.328us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 898.310s 10453.522us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 452.420s 5525.593us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 63.750s 3114.146us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 227.270s 4466.783us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1380.810s 21455.571us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 381.310s 8276.762us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 151.430s 3555.540us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1467.170s 22498.410us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 642.730s 7488.036us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1239.620s 14079.609us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1916.980s 28923.331us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 128.520s 2799.930us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 426.810s 5438.307us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 383.420s 8927.899us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 383.420s 8927.899us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 1239.620s 14079.609us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1467.170s 22498.410us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 452.420s 5525.593us 1 1 100.00
chip_sw_pwrmgr_smoketest 348.360s 5328.380us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 235.560s 4511.748us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 387.970s 5462.200us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 307.500s 4530.009us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1144.320s 13794.484us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 165.180s 3293.611us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 426.810s 5438.307us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 909.730s 7536.572us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 492.840s 5215.737us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 521.800s 4667.987us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 173.420s 3375.029us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 146.750s 3061.126us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 387.970s 5462.200us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 387.970s 5462.200us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1337.520s 16984.173us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 863.480s 13274.989us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 235.560s 4511.748us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 213.100s 2758.929us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 323.470s 7546.190us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 98.920s 3278.478us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 288.690s 10300.617us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 587.900s 5868.730us 1 1 100.00
chip_plic_all_irqs_10 319.590s 3882.813us 1 1 100.00
chip_plic_all_irqs_20 308.690s 3806.264us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 171.810s 3437.265us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 164.630s 3114.247us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2960.030s 15183.456us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 538.730s 7682.632us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 195.030s 3580.909us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 265.580s 3617.207us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 150.950s 2886.082us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 497.610s 5761.484us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 363.070s 5156.245us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 355.170s 6436.208us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 342.610s 7306.253us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 486.760s 9403.537us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 426.810s 5438.307us 1 1 100.00
chip_sw_data_integrity_escalation 438.800s 5358.663us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 642.730s 7488.036us 1 1 100.00
chip_sw_sysrst_ctrl_reset 970.000s 23534.466us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 132.480s 2940.110us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 238.030s 3448.347us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 361.770s 4307.360us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 970.000s 23534.466us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 970.000s 23534.466us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2380.750s 20271.944us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2380.750s 20271.944us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 233.530s 5428.651us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2924.570s 34694.274us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 142.160s 2708.563us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 185.490s 2772.136us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 304.300s 3537.589us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 307.580s 4238.203us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 960.020s 8166.723us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5143.880s 31876.445us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1759.010s 11888.189us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 133.780s 2740.472us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 164.240s 2418.423us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 121.260s 2392.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 10281.100s 71673.254us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1089.220s 7019.030us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 371.670s 6242.900us 0 1 0.00
rom_e2e_jtag_debug_dev 152.460s 4514.555us 0 1 0.00
rom_e2e_jtag_debug_rma 397.160s 6340.301us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 55.520s 2280.459us 0 1 0.00
rom_e2e_jtag_inject_dev 73.800s 2598.912us 0 1 0.00
rom_e2e_jtag_inject_rma 65.690s 2370.923us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 122.386s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 315.630s 3443.302us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 324.740s 2835.114us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 870.700s 5337.948us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 884.660s 6634.223us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 266.280s 2892.612us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 522.830s 5950.117us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 152.330s 2948.148us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 158.680s 3665.771us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 248.250s 6417.931us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 260.830s 4766.697us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1239.620s 14079.609us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 371.670s 6242.900us 0 1 0.00
rom_e2e_jtag_debug_dev 152.460s 4514.555us 0 1 0.00
rom_e2e_jtag_debug_rma 397.160s 6340.301us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 337.370s 5531.494us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 426.810s 5438.307us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5560.240s 38466.701us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5560.240s 38466.701us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 153.670s 3734.461us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 366.380s 4290.251us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2948.800s 18953.242us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 10 70.00
chip_sival_flash_info_access 180.320s 3096.195us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 326.060s 5422.144us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 5.770s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 126.360s 2377.895us 1 1 100.00
chip_sw_otp_ctrl_descrambling 199.220s 3012.708us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 189.750s 3160.770us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 9.534s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 198.080s 3750.293us 1 1 100.00
ate_bootstrap_flash_erase 6280.630s 44867.136us 1 1 100.00
ate_bootstrap_disjoint 10093.460s 84564.910us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 27932667162494691578868717967300217485406094214237292172204139077897480215034 320
UVM_INFO @ 3580.908656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 31672843046370258257235741478965922361299810990692128406333635206200605074728 309
UVM_INFO @ 2826.891964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 105495452053004277999990027114127050842832206184921639406748421797834962789237 342
UVM_INFO @ 6526.016774 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 49641733160636111205861720095047929755402902014727638513402322184939734522565 316
UVM_ERROR @ 3665.771060 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3665.771060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 110316753872912763334455237015347397586416007692552349399104563615481898642844 312
UVM_ERROR @ 2490.207356 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2490.207356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 79564317198453984257600228804657918238458968743381070712415119910312530193196 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 6053441117914715596048622218214332675613458907976380757621609743916769425957 369
UVM_INFO @ 8196.786809 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 56496476915051140314657623176471034298882586184141958703314331734128437462958 369
UVM_INFO @ 9943.778086 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 75684248441465805392937745119227858567341040893707779972473936089018238365249 341
UVM_INFO @ 5695.215750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'
chip_sw_pwrmgr_full_aon_reset 64107617291244140417897101213977680293469761130646148958527290805002496320084 303
UVM_ERROR @ 3114.146348 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 3114.146348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 46773311657800646060230072752862737042394312736003468107642792650951435338733 314
UVM_ERROR @ 6218.976000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6218.976000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 40831146248539313083520140165236549149332151477758252037669329329919334791109 325
UVM_ERROR @ 7393.516000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7393.516000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 32655691836144875655103172768394132788341634707002841232735069478166480576027 410
UVM_ERROR @ 21455.571500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 21455.571500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 114274774669871664896754425430969753682626372063951361426856046210932440240457 319
UVM_ERROR @ 7967.328000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7967.328000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'
chip_sw_pwrmgr_sleep_power_glitch_reset 60939497351420365360134686202148969472078571758333421413493081164272339702943 313
UVM_ERROR @ 3555.539985 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3555.539985 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 22108528490275414533559133586863030724074660280798287874473777431184941109379 332
UVM_INFO @ 34694.273899 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!
chip_sw_alert_test 103217732830379040538908050656417231597080019759593549260209803329807388780718 307
UVM_INFO @ 3544.891920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 43874092284764841770743006791270885278770750549555332055287478911831052274316 308
UVM_INFO @ 3345.915055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
chip_sw_alert_handler_lpg_sleep_mode_pings 61369635925980051915447657443373326228447238241218765884759753808710964445538 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 82439908884712487831830222235225922721012195086360153526635839254405686951300 218
TL item was: req: (cip_tl_seq_item@184089) { a_addr: 'h107e4 a_data: 'h24a5b44e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1a a_opcode: 'h4 a_user: 'h195a0 d_param: 'h0 d_source: 'h1a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 4162.731195 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 106006515867816580702363094308670126597981516203736795304206450765798777466386 224
TL item was: req: (cip_tl_seq_item@31955) { a_addr: 'h10368 a_data: 'hd90326e1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h13 a_opcode: 'h4 a_user: 'h1ae57 d_param: 'h0 d_source: 'h13 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2218.122518 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 18947220911435584945040561301991905527152143460992722797881733771964980784574 343
UVM_INFO @ 3443.301660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()
chip_sw_pwrmgr_lowpower_cancel 64944200706774464169584034950517909731528401158664027739211906778677936550158 311
UVM_INFO @ 3160.770292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
chip_sw_pwrmgr_sleep_wake_5_bug 39186677110693749824823235122986301651874019034394631256647176115964927414656 None
---- STDERR ----
Another command (pid=2085238) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 6795720487272280840655415276769484608671628893225799302531932510983589143165 None
Another command (pid=436976) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=369905) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=374421) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 101885317185734608104187904530256439984073531952433838346489975790022783155908 None
---- STDERR ----
Another command (pid=538762) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=551354) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 18823439859331964118398766922703142152989754326715839720404880216641166844096 None
Another command (pid=556580) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=529138) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=560426) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 91952168047366330199182735645573396707125834496341794381008478496081285382248 None
Another command (pid=556349) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=409481) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=529138) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 3364058188351218485664797342050420033967918191333363860106434047567260420049 None
---- STDERR ----
Another command (pid=538762) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 29627139315890629281891222399683260148875974752628333540369347976930160692293 None
Another command (pid=436738) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=436976) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=369905) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 97416905712019798197418424322945989631633459133106524752041492434613302106728 None
Another command (pid=539117) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=392484) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=415105) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 36199631687774258941493731592436346630519873371456925359851808740051568100723 None
Another command (pid=529138) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=560426) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=407751) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 23526855330297452748707779082947143500567179091485407469779100917561435642056 None
---- STDERR ----
Another command (pid=437585) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 104765719783631260453682023738375898699734585145869715769291945960704550343451 None
Another command (pid=538762) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=551354) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=409481) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 31698804233492406599984436962773037549183306059627025065517235856610836009068 None
---- STDERR ----
Another command (pid=386024) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 71552399624200672319074266487932057604681224842939323253347956618329774665135 None
Another command (pid=437585) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=436738) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=362183) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 60018393072036509245285187801026863485801215965858796617591256388406978442933 None
Another command (pid=560426) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=407751) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=557688) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 14340910792000589116061502514719041698706045691990070322711121558868916121670 None
Another command (pid=567064) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=565512) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=559131) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 37468223338510945853410560707206509608032152270894296871923655438162001188546 None
Another command (pid=797804) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=774950) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=801655) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 57821363738482775314059660602983295835852614036054669299815550736527467122424 None
Another command (pid=437585) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=436738) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=436976) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 13485785448839175290637796485230847078505755249407856836403969467664089542320 None
---- STDERR ----
Another command (pid=358866) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 51503017198956334958503516976221290768113552547775528095367155016967505627270 None
Another command (pid=402033) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=371372) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=386024) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 115312155833148656730728798652260755926503975684958398960613284660100016226473 None
---- STDERR ----
Another command (pid=358866) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=392715) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 78115728310616090339701533894400357595476173910532653070242953454752913584046 None
---- STDERR ----
Another command (pid=371372) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=386024) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 4093743950934574276077410460802174271753214311522847732958367260432064424760 None
Another command (pid=380589) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=466592) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=539117) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 89876178667774796351471020296585949711083965220998162304690589423854883654164 None
Another command (pid=380589) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=466592) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=539117) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 95663204306562593405130898113249074164830328491980733106207312104407124790231 None
Another command (pid=536854) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=380589) is running. Waiting for it to complete on the server (server_pid=264452)...
Another command (pid=466592) is running. Waiting for it to complete on the server (server_pid=264452)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 13754097727820225072115332012729443949975243800937724259137031640820556919127 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 83140707546232460426079361080534578403845691832827275030679038154050587663001 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 93983818871490308903426529345901007731205225356509333405717342653917922015474 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 85280284566572623513087069963378096167660676850007219003366003020745490254498 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 15237144609118727350358116151335993847856782581427997792777997352929509354398 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 64524628244835038054357632160502009485895741438427758891490824423861423588626 305
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 81512449474146523443616277783793582147455970267633886231398569337883779465785 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 101034171018531106723661721110744804499680249374393116414355982020188187431118 258
UVM_INFO @ 10300.617355 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 79768069101945786986398004171187004491253689600616187082674859595066809321379 312
UVM_INFO @ 3350.440000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 74763573268963905350176191156570973655099507265329306869055380577130300082889 318
UVM_INFO @ 2785.410000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 57745519501534536691974562026246311434318718019672138786239695953680451906592 327
UVM_INFO @ 10811.939190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 81944030238973379596653624058679911365739533040555858485956607709950088765487 365
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 94129130097402908322457327155455958539389847870820046243788187526298189207586 325
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 101446688714303231301356448466388420641945654460909224295245192050179645869640 368
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 84626038507118010021405065356805284430876043882272422054874968377280798150950 328
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_prod 56999996690665313778327800111297690840972432287856797001795878873234552240294 368
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 78176203780079155505121118822123105744514942957040699592385326443058786298175 366
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 63808071575756251221806345698624937872842581235940390068769461259301516609426 367
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 25709499933105958079293672918649981912627623369189209449171357567984356323487 327
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 36337080096737444913073474167917959224327856268639577200897733831120646402220 328
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 86228954676387754270234396308786640687503964641730939576909074139005970259771 326
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 74061868844891723297756285753946171797081225873156160434578899043839312418196 325
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 76862647531160791008707966245621322224448221365462280364300135423963104658436 328
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 61253143928738929896146300867780942595795659906908265819513580144466223446923 326
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 89043809350032474854180572674585136830735260343023285259145567987515201654962 327
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 26602892841340094243077823589378140317290872934771137275421653234163819921870 328
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_no_meas 31136375248603173364719979573607335147102623450131434480854328791067072289907 319
UVM_INFO @ 17149.071864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 57686955418235139013211664513564822657503756326802442697812590083660707676066 327
UVM_ERROR @ 5429.748836 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5429.748836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---