Simulation Results: clkmgr

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.56 %
  • code
  • 98.24 %
  • assert
  • 95.48 %
  • func
  • 86.96 %
  • line
  • 98.99 %
  • branch
  • 98.62 %
  • cond
  • 94.40 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.910s 75.589us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.760s 27.168us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.820s 21.342us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 2.580s 144.330us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.120s 42.883us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.380s 40.885us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.820s 21.342us 1 1 100.00
clkmgr_csr_aliasing 1.120s 42.883us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.770s 15.512us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 2.420s 569.958us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.700s 28.401us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.070s 54.721us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.910s 75.589us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 11.040s 2118.288us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 2.270s 505.853us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 11.040s 2118.288us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 1.410s 325.186us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.780s 18.722us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.640s 103.976us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.640s 103.976us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.760s 27.168us 1 1 100.00
clkmgr_csr_rw 0.820s 21.342us 1 1 100.00
clkmgr_csr_aliasing 1.120s 42.883us 1 1 100.00
clkmgr_same_csr_outstanding 0.840s 28.874us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.760s 27.168us 1 1 100.00
clkmgr_csr_rw 0.820s 21.342us 1 1 100.00
clkmgr_csr_aliasing 1.120s 42.883us 1 1 100.00
clkmgr_same_csr_outstanding 0.840s 28.874us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 2.090s 410.426us 0 1 0.00
clkmgr_tl_intg_err 1.630s 195.139us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.090s 117.488us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.090s 117.488us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.090s 117.488us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.090s 117.488us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.720s 735.778us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.630s 195.139us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 11.040s 2118.288us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 2.270s 505.853us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.090s 117.488us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.900s 65.051us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.800s 47.833us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.690s 17.313us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.720s 24.326us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.740s 29.382us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.820s 21.342us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 2.090s 410.426us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.820s 21.342us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.820s 21.342us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 2.090s 410.426us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.380s 1192.505us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 106.890s 29309.122us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 59068239201399069335407705885194433441583949411391376145761388721967535033473 216
UVM_INFO @ 410426173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---