Simulation Results: edn/edn0

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.19 %
  • code
  • 84.05 %
  • assert
  • 96.96 %
  • func
  • 80.56 %
  • line
  • 98.32 %
  • branch
  • 94.14 %
  • cond
  • 88.57 %
  • toggle
  • 85.45 %
  • FSM
  • 53.76 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.880s 16.984us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 36.426us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.920s 12.911us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.530s 39.696us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.040s 44.221us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.340s 25.208us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.920s 12.911us 1 1 100.00
edn_csr_aliasing 1.040s 44.221us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.140s 32.989us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.140s 32.989us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.140s 32.989us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.030s 25.913us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.200s 25.117us 1 1 100.00
errs 1 1 100.00
edn_err 0.850s 25.613us 1 1 100.00
disable 2 2 100.00
edn_disable 0.790s 23.577us 1 1 100.00
edn_disable_auto_req_mode 0.890s 79.302us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.840s 493.353us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.830s 33.999us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.890s 52.310us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.120s 30.889us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.120s 30.889us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.860s 36.426us 1 1 100.00
edn_csr_rw 0.920s 12.911us 1 1 100.00
edn_csr_aliasing 1.040s 44.221us 1 1 100.00
edn_same_csr_outstanding 1.020s 21.529us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.860s 36.426us 1 1 100.00
edn_csr_rw 0.920s 12.911us 1 1 100.00
edn_csr_aliasing 1.040s 44.221us 1 1 100.00
edn_same_csr_outstanding 1.020s 21.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.610s 3990.235us 1 1 100.00
edn_tl_intg_err 1.330s 113.803us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.940s 29.853us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.200s 25.117us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.610s 3990.235us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.610s 3990.235us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.610s 3990.235us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.610s 3990.235us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.200s 25.117us 1 1 100.00
edn_sec_cm 6.610s 3990.235us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.200s 25.117us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.330s 113.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 28.500s 3858.851us 1 1 100.00