Simulation Results: edn/edn1

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.29 %
  • code
  • 84.49 %
  • assert
  • 97.14 %
  • func
  • 80.25 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 89.62 %
  • toggle
  • 95.70 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.790s 17.521us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.960s 62.550us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.890s 17.076us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.090s 173.292us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.950s 97.078us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.230s 53.048us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.890s 17.076us 1 1 100.00
edn_csr_aliasing 0.950s 97.078us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.920s 83.380us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.920s 83.380us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.920s 83.380us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.850s 42.487us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.920s 25.257us 1 1 100.00
errs 1 1 100.00
edn_err 0.990s 26.337us 1 1 100.00
disable 2 2 100.00
edn_disable 0.730s 18.595us 1 1 100.00
edn_disable_auto_req_mode 0.990s 36.207us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.480s 292.831us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.780s 24.385us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.810s 21.946us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.260s 147.572us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.260s 147.572us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.960s 62.550us 1 1 100.00
edn_csr_rw 0.890s 17.076us 1 1 100.00
edn_csr_aliasing 0.950s 97.078us 1 1 100.00
edn_same_csr_outstanding 0.860s 116.218us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.960s 62.550us 1 1 100.00
edn_csr_rw 0.890s 17.076us 1 1 100.00
edn_csr_aliasing 0.950s 97.078us 1 1 100.00
edn_same_csr_outstanding 0.860s 116.218us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.130s 601.732us 1 1 100.00
edn_tl_intg_err 1.410s 187.299us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.760s 27.548us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.920s 25.257us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.130s 601.732us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.130s 601.732us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.130s 601.732us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.130s 601.732us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.920s 25.257us 1 1 100.00
edn_sec_cm 2.130s 601.732us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.920s 25.257us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.410s 187.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 19.240s 4177.968us 1 1 100.00