Simulation Results: flash_ctrl

 
28/04/2026 15:30:29 DVSim: v1.32.0 sha: f8cd0a3 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.32 %
  • code
  • 93.06 %
  • assert
  • 94.28 %
  • func
  • 95.63 %
  • line
  • 95.89 %
  • branch
  • 96.64 %
  • cond
  • 92.93 %
  • toggle
  • 94.79 %
  • FSM
  • 85.03 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 49.760s 31.024us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 10.320s 16.200us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 23.220s 46.925us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.230s 158.983us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 48.320s 4575.671us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 23.690s 851.725us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.620s 69.198us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.230s 158.983us 1 1 100.00
flash_ctrl_csr_aliasing 23.690s 851.725us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 12.310s 29.141us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.860s 34.271us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.350s 48.309us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 11.130s 22.492us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1251.800s 1318704.285us 1 1 100.00
flash_ctrl_hw_rma_reset 585.350s 160187.974us 1 1 100.00
flash_ctrl_lcmgr_intg 5.960s 41.861us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1545.900s 235775.491us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 171.550s 12663.447us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 7.840s 256.494us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1807.630s 313043.318us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 71.510s 2905.817us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 20.170s 121.574us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.490s 76.921us 1 1 100.00
flash_ctrl_re_evict 16.620s 64.330us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 88.280s 132.508us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 88.280s 132.508us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 118.700s 22989.262us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 17.380s 326.425us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 83.530s 83.331us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 392.630s 33016.481us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 332.300s 1265.404us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 691.900s 561.813us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 8.580s 23.248us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 125.670s 1396.259us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 8.540s 19.019us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.600s 55.750us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 478.000s 339.614us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 176.650s 15619.184us 1 1 100.00
flash_ctrl_otp_reset 54.460s 158.199us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1251.800s 1318704.285us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 119.470s 8030.889us 1 1 100.00
flash_ctrl_intr_wr 51.780s 2856.335us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 132.040s 17760.060us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 168.610s 58205.011us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 42.940s 3057.719us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 40.970s 880.246us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.030s 82.835us 1 1 100.00
flash_ctrl_ro_derr 88.760s 2676.936us 1 1 100.00
flash_ctrl_rw_derr 113.500s 1132.572us 1 1 100.00
flash_ctrl_derr_detect 130.630s 1299.642us 1 1 100.00
flash_ctrl_integrity 407.240s 3729.392us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.810s 37.719us 1 1 100.00
flash_ctrl_ro_serr 91.260s 2893.709us 1 1 100.00
flash_ctrl_rw_serr 176.280s 8157.810us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 40.900s 1677.111us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 65.970s 1261.693us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 171.500s 3283.942us 1 1 100.00
flash_ctrl_write_word_sweep 6.820s 518.469us 1 1 100.00
flash_ctrl_read_word_sweep 5.790s 28.115us 1 1 100.00
flash_ctrl_ro 84.680s 559.886us 1 1 100.00
flash_ctrl_rw 414.570s 8409.442us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 23.730s 652.124us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 573.800s 41783.573us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 95.580s 10019.212us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.830s 47.094us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 8.540s 16.727us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.450s 114.331us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.450s 114.331us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 23.220s 46.925us 1 1 100.00
flash_ctrl_csr_rw 9.230s 158.983us 1 1 100.00
flash_ctrl_csr_aliasing 23.690s 851.725us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.950s 164.672us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 23.220s 46.925us 1 1 100.00
flash_ctrl_csr_rw 9.230s 158.983us 1 1 100.00
flash_ctrl_csr_aliasing 23.690s 851.725us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.950s 164.672us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 32.220s 76.403us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 32.220s 76.403us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 32.220s 76.403us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 32.220s 76.403us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 23.590s 1197.907us 1 1 100.00
tl_intg_err 1 2 50.00
flash_ctrl_sec_cm 1636.540s 200000.000us 0 1 0.00
flash_ctrl_tl_intg_err 272.460s 2752.111us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 272.460s 2752.111us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 272.460s 2752.111us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.550s 86.496us 1 1 100.00
flash_ctrl_wr_intg 7.040s 70.004us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 49.760s 31.024us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 54.460s 158.199us 1 1 100.00
flash_ctrl_disable 8.540s 19.019us 1 1 100.00
flash_ctrl_sec_info_access 41.510s 1286.013us 1 1 100.00
flash_ctrl_connect 7.600s 55.750us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 7.310s 41.657us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.230s 158.983us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 32.220s 76.403us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.230s 158.983us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 32.220s 76.403us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.230s 158.983us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 32.220s 76.403us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 8.540s 19.019us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.550s 86.496us 1 1 100.00
flash_ctrl_access_after_disable 5.780s 20.262us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 18.570s 47.306us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 8.540s 19.019us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 17.380s 326.425us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 414.570s 8409.442us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 176.280s 8157.810us 1 1 100.00
flash_ctrl_rw_derr 113.500s 1132.572us 1 1 100.00
flash_ctrl_integrity 407.240s 3729.392us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1251.800s 1318704.285us 1 1 100.00
sec_cm_ctrl_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 1636.540s 200000.000us 0 1 0.00
sec_cm_phy_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 1636.540s 200000.000us 0 1 0.00
sec_cm_phy_prog_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 1636.540s 200000.000us 0 1 0.00
sec_cm_ctr_redun 0 1 0.00
flash_ctrl_sec_cm 1636.540s 200000.000us 0 1 0.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 11.760s 741.233us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 0 1 0.00
flash_ctrl_phy_host_grant_err 5.920s 22.213us 0 1 0.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.290s 118.026us 1 1 100.00
sec_cm_fifo_ctr_redun 0 1 0.00
flash_ctrl_sec_cm 1636.540s 200000.000us 0 1 0.00
sec_cm_mem_tl_lc_gate_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 1636.540s 200000.000us 0 1 0.00
sec_cm_prog_tl_lc_gate_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 1636.540s 200000.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 19.160s 127.692us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 211.140s 426.717us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue
flash_ctrl_sec_cm 53891817310291014434756610041321107805032409134383148776507714332685479762322 4103
UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
flash_ctrl_phy_host_grant_err 66329286963950775392100625478599871394230898161324309598448399362616332846846 125
UVM_ERROR @ 22213.1 ns: (alert_esc_if.sv:201) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 22213.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---